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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

feat(topdown): add OoO-window bottleneck attribution module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#6173 opened Jun 30, 2026 by lewislzh Member • Draft
fix(divsqrt): return canonical qNaN when operands are not NaN-boxed module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6172 opened Jun 30, 2026 by emiliengnr Loading…
2
docs: add CONTRIBUTING module: documentation Improvements or additions to documentation module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc.
#6171 opened Jun 30, 2026 by ngc7331 Member Loading…
1
submodule: bump XSCache module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6170 opened Jun 30, 2026 by Frankslu Contributor Loading…
1
fix(IPrefetch): do not send ITLB req if pipeline s1 stalled module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#6169 opened Jun 29, 2026 by ngc7331 Member • Draft
fix(Ittage): fix altDiffer condition module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6167 opened Jun 29, 2026 by ngc7331 Member • Draft
1
perf(MemBlock): optimize L1DCache index module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#6166 opened Jun 29, 2026 by Frankslu Contributor Loading…
8
fix(MMU): use SPVP mode for HLV, HLVX, and HSV PMP checks module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6164 opened Jun 28, 2026 by fuhuakai Loading…
1
fix(vbop): use the correct handshake logic and tidy coding module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6163 opened Jun 28, 2026 by Maxpicca-Li Member • Draft
1 task
1
fix(pmp): support 64 pmp module: other ChiselAIA, IMSIC, CLINT, etc. module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6136 opened Jun 25, 2026 by sinceforYy Contributor • Draft
fix(vstopi): fix the mapping of vsei index module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6131 opened Jun 24, 2026 by sinceforYy Contributor Loading…
8
fix(sstc): menvcfg.stce shouldn't control an attempt to access vstimecmp module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6129 opened Jun 24, 2026 by wissygh Contributor • Draft
fix(stopi): fix siprios should be masked by sie or hie module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6128 opened Jun 24, 2026 by sinceforYy Contributor Loading…
2
fix(aia): mstateen0.AIA shouldn't have effect on attempts in VS-mode to access sireg module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6125 opened Jun 24, 2026 by wissygh Contributor • Draft
1
Kunminghu v3 dcache dual port module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#6124 opened Jun 24, 2026 by Ruomio Contributor Loading…
1
feat: integrate ZhuJiang single-core topology module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6122 opened Jun 23, 2026 by linjuanZ Member • Draft
1
fix(perf): fixed perf-event frontend_stall_cycle module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6121 opened Jun 23, 2026 by wissygh Contributor Loading…
1
Timing/raw oldest age matrix module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: timing To fix bad timing
#6120 opened Jun 23, 2026 by zzQGyy Contributor Loading…
1
feat(MMU): add ptehelper support module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#6115 opened Jun 21, 2026 by fuhuakai Loading…
1
feat(ifu): add a resolve feedback path from the IFU to the BPU for training module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#6112 opened Jun 18, 2026 by my-mayfly Collaborator • Draft
1
fix(debug, csr): fix csr to support debug spec 1.0 module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6104 opened Jun 17, 2026 by wissygh Contributor Loading…
1
timing(L1PrefetchComponent): defer sent_vec updates to pf fire module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#6102 opened Jun 17, 2026 by zzQGyy Contributor Loading…
1
fix(CSR): fix reset value of mstatus.mdt & mnstatus.nmie module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6100 opened Jun 16, 2026 by wissygh Contributor • Draft
fix(TopDown): fix memStall module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6097 opened Jun 15, 2026 by sinceforYy Contributor Loading…
1
feat(LoadQueueReplay): add support of fast wakeup for C_MA & C_FF module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6092 opened Jun 13, 2026 by weidingliu Member Loading…
1
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