fix(divsqrt): return canonical qNaN when operands are not NaN-boxed#6172
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emiliengnr wants to merge 1 commit into
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fix(divsqrt): return canonical qNaN when operands are not NaN-boxed#6172emiliengnr wants to merge 1 commit into
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Thank you for your contribution. We have a draft contributing guidelines that you might want to refer to: Lines 64 to 77 in 69fa610 For the current PR, please change the PR title to the conventional commits format (i.e., |
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Thank you for the pointer to the guidelines, I updated the title and body of the pull request and the commit message. |
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fix(divsqrt): return canonical qNaN when operands are not NaN-boxed
Hello, here is a pull request for a bug I found.
Two execution units in XiangShan write their floating-point results onto the same shared output port (FP writeback port 6). One of them, the vector-float unit VFEX0, has a fixed pipeline timing and physically cannot wait its turn. When a load happens to deliver its own result on the same cycle, the load wins the shared port and VFEX0's result is thrown away. In simulation, this trips an assertion and stops the run. In real silicon, where that assertion is gone, the floating-point register write simply vanishes and the program computes the wrong answer. An earlier upstream change, PR #3363, added a one-cycle latency to vector-float writebacks to the FP register file, but it does not prevent this collision: the unit VFEX0 contends with is an uncertain-latency load in a different scheduler, whose writeback cycle cannot be reserved against by any latency adjustment. The fix is to remove the sharing. Give VFEX0 its own private writeback port (port 8) so it never has to compete for the shared one. Every other fixed-timing FP producer in the design already owns a private port.
Severity: Assertion crash and silent data loss. A fixed-latency FP result is dropped. Under
--diffthis shows up as a regfile mismatch followed byABORT. In synthesized hardware with the assertion compiled out it becomes a silently lost FP register write.