Skip to content

fix(divsqrt): return canonical qNaN when operands are not NaN-boxed #6172

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
emiliengnr wants to merge 1 commit into
base: kunminghu-v3
Choose a base branch
from
+3 −1
Open

fix(divsqrt): return canonical qNaN when operands are not NaN-boxed #6172

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 3 additions & 1 deletion src/main/scala/xiangshan/Parameters.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -429,7 +429,9 @@ case class XSCoreParameters
ExeUnitParams(
"VFEX0",
Seq(VialuCfg, VfaluCfg, VfmaCfg, VimacCfg, VppuCfg, VipuCfg, VfcvtCfg, VSetRvfWvfCfg, VmoveCfg),
Seq(VfWB(port = 0, 0), V0WB(port = 0, 0), IntWB(port = 4, 1), FpWB(port = 6, 0)),
// VFEX0 has fixed latency and cannot stall on writeback, so give it a
// private FP port 8 instead of sharing port 6 with the load unit LDU2.
Seq(VfWB(port = 0, 0), V0WB(port = 0, 0), IntWB(port = 4, 1), FpWB(port = 8, 0)),
Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0))),
vlWB = VlWB(port = vfSchdVlWbPort, 0),
vlRD = VlRD(0, 0),
Expand Down
Loading