feat(MMU): add ptehelper support#6115
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Emu - Performance SummaryMetadata
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Update the difftest submodule to the ptehelper DPI model used by the MMU simulation helper. The bumped difftest commit provides the PTEHelper Verilog wrapper, the pte_helper C++ walk model, PBMT and NAPOT fault handling, and TLB checker diagnostic output needed by the matching RTL change. This commit only updates the submodule gitlink. The actual RTL support is added in the next commit.
Add ptehelper as a DPI-C backed ideal translation path for MMU simulation studies. The feature can bypass selected hardware translation structures and use a software page-table walk model to evaluate the MMU translation performance upper bound. softTLB replaces the L1 TLB storage with TLBFakeFA. The fake storage returns a registered helper result on the cycle after a valid request when translation is enabled, and it does not take the normal TLB miss and refill path. softPTW replaces the normal L2TLB implementation at the L2TLBWrapper boundary with FakePTW. From the L1 TLB side this bypasses the L2TLB, page-table cache, and PTW miss path, while still returning the normal L2TLBIO response format. Add PTEHelper, PteHelperResult, and shared response builders so the softTLB and softPTW paths use the same PPN, permission, PBMT, NAPOT, and stage-fault construction. The helper covers Sv39, Sv48, Sv39x4, Sv48x4, PBMTE-gated PBMT checks, and two-stage translation results. The softPTW path also avoids instantiating the normal PTW-to-L2 buffer module in the reset tree when the normal L2TLB path is disabled. The feature is controlled by the existing softTLB and softPTW fields in core parameters. Both flags stay disabled by default. Validated with rvh-test using softTLB and softPTW modes. Both modes pass all rvh-test cases, including PBMT tests.
Rename the misspelled EnbaleTlbDebug parameter and its users to EnableTlbDebug. This keeps the debug switch name readable without changing the generated logic.
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Add ptehelper as a DPI-C backed ideal translation path for MMU
simulation studies. The feature can bypass selected hardware
translation structures and use a software page-table walk model to
evaluate the MMU translation performance upper bound.
softTLB replaces the L1 TLB storage with TLBFakeFA. The fake storage
returns a registered helper result on the cycle after a valid request
when translation is enabled, and it does not take the normal TLB miss
and refill path.
softPTW replaces the normal L2TLB implementation at the L2TLBWrapper
boundary with FakePTW. From the L1 TLB side this bypasses the L2TLB,
page-table cache, and PTW miss path, while still returning the normal
L2TLBIO response format.
Add PTEHelper, PteHelperResult, and shared response builders so the
softTLB and softPTW paths use the same PPN, permission, PBMT, NAPOT,
and stage-fault construction. The helper covers Sv39, Sv48, Sv39x4,
Sv48x4, PBMTE-gated PBMT checks, and two-stage translation results.
The softPTW path also avoids instantiating the normal PTW-to-L2 buffer
module in the reset tree when the normal L2TLB path is disabled.
The feature is controlled by the existing softTLB and softPTW fields in
core parameters. Both flags stay disabled by default.
Without enabling softtlb/softptw, it will not affect any of the original hardware logic.
Validated with rvh-test using softTLB and softPTW modes. Both modes
pass all rvh-test cases, including PBMT tests.