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fix(sstc): menvcfg.stce shouldn't control an attempt to access vstimecmp #6129

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fix(sstc): menvcfg.stce shouldn't control an attempt to access vstimecmp #6129

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f6448c4
fix(sstc): menvcfg.sstc shouldn't control an attempt to access vstimecmp
wissygh Jun 24, 2026
a331d64
submodule(ready-to-run): bump ready-to-run to fix sstc
wissygh Jun 24, 2026
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2 changes: 1 addition & 1 deletion ready-to-run
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Submodule ready-to-run updated 4 files
+ − riscv64-nemu-interpreter-debug-so
+ − riscv64-nemu-interpreter-dual-debug-so
+ − riscv64-nemu-interpreter-dual-so
+ − riscv64-nemu-interpreter-so
6 changes: 4 additions & 2 deletions src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -222,7 +222,9 @@ class MLevelPermitModule extends Module {

private val fpVec_EX_II = fpOff_EX_II || vecOff_EX_II

private val rwStimecmp_EX_II = !privState.isModeM && (!mcounterenTM || !menvcfgSTCE) && (addr === CSRs.vstimecmp.U || addr === CSRs.stimecmp.U)
private val rwStimecmp_EX_II = !privState.isModeM &&
(!mcounterenTM && (addr === CSRs.vstimecmp.U || addr === CSRs.stimecmp.U) ||
!menvcfgSTCE && (addr === CSRs.stimecmp.U))

private val accessHPM_EX_II = csrIsHPM && !privState.isModeM && !mcounteren(counterAddr)

Expand Down Expand Up @@ -612,7 +614,7 @@ class xcounterenIO extends Bundle {

class xenvcfgIO extends Bundle {
// Machine environment configuration register.
// Accessing stimecmp or vstimecmp from **Non-M level** will trap EX_II, if menvcfg.STCE=0
// Accessing stimecmp from **Non-M level** will trap EX_II, if menvcfg.STCE=0
val menvcfg = UInt(64.W)
// Hypervisor environment configuration register.
// Accessing vstimecmp from ** V level** will trap EX_VI, if menvcfg.STCE=1 && henvcfg.STCE=0
Expand Down
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