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cpu-o3, mem-cache: Model L1D fake DCache mainpipe #912

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Merged
XXtaoo merged 9 commits into from
Jun 26, 2026
Merged

cpu-o3, mem-cache: Model L1D fake DCache mainpipe #912

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116f5eb
cpu-o3: Add LSQ-local fake DCache mainpipe
XXtaoo Jun 2, 2026
e66bfa9
mem-cache: Model L1D refill MSHR availability with fake mainpipe
XXtaoo Jun 8, 2026
1653c7a
cpu-o3: Issue SBuffer evictions from fake DCache MainPipe S2
XXtaoo Jun 4, 2026
272b847
cpu-o3: Add fake mainpipe blocking stats
XXtaoo Jun 10, 2026
881cfa0
mem-cache: Route prefetch refills through fake mainpipe
XXtaoo Jun 11, 2026
dcf2316
mem-cache: Count L1D fill updates in fake mainpipe
XXtaoo Jun 12, 2026
1b4ecd7
cpu-o3: Align fake dcache mainpipe timing
XXtaoo Jun 18, 2026
956a8d3
cpu-o3: Refine fake mainpipe admission timing
XXtaoo Jun 18, 2026
52dcc9c
cpu-o3: Fix fake mainpipe refill tag write blocking
XXtaoo Jun 25, 2026
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13 changes: 7 additions & 6 deletions src/cpu/o3/issue_queue.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -498,9 +498,9 @@ IssueQue::issueToFu()
auto& inst = replayQ.front();

if (inst->isLoad()) {
// Check if tag write is happening in the next cycle
// if so, load cannot be issued to load pipeline
if (scheduler->lsq->isDcacheRefillTagWrite()) {
// Loads selected here enter loadpipe S0 next cycle, so block on
// the mainpipe tag-write state predicted for that admission point.
if (scheduler->lsq->willDcacheRefillTagWriteNextCycle()) {
incTagRefillBlockStats = true;
break;
}
Expand All @@ -527,9 +527,10 @@ IssueQue::issueToFu()
if (!inst) {
continue;
}
// Check if tag write is happening in the next cycle
// if so, load cannot be issued to load pipeline
bool blockLoad = inst->isLoad() && scheduler->lsq->isDcacheRefillTagWrite();
// Loads selected here enter loadpipe S0 next cycle, so block on
// the mainpipe tag-write state predicted for that admission point.
bool blockLoad = inst->isLoad() &&
scheduler->lsq->willDcacheRefillTagWriteNextCycle();
if (blockLoad) {
incTagRefillBlockStats = true;
}
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