cpu-o3, mem-cache: Model L1D fake DCache mainpipe#912
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Replace the old per-div refill bitmask model with an LSQ-local fake DCache MainPipe that models refill and store-buffer resource blocking. The fake pipe keeps S1/S2/S3 state, uses refill priority over store-buffer requests, models same-set hazards, refill tag-write blocking, and S1 data-read versus S3 data-write bank conflicts. Gate store-buffer writeback through the fake MainPipe before sending to the classic cache, while keeping MainPipe-local blocking separate from classic-cache port blocking. Derive load bank occupancy from fake MainPipe S1/S3 resource usage and add stats for refill/store admission and blocking causes. The classic cache remains the real memory access path; this MainPipe is only a timing/resource blocking model. Change-Id: I1e9957e34042bfd3162bbdecdae297a59aa31e31
Keep the classic cache refill response path functional while delaying the effective availability of released L1D MSHR entries through the LSQ-local fake DCache mainpipe. The refill response still services CPU targets when data returns, but the freed MSHR capacity is held by a fake credit until the refill leaves the fake mainpipe. This models refill mainpipe occupancy without moving actual cache accesses out of the classic cache path. Sample the pre-release MSHR-full state before taking the fake credit so cache retry/unblock state is updated only when effective MSHR capacity is really released. Change-Id: I4a0b5ad7825deb49ac65fc84f00462997f72c2b0
Delay StoreBuffer classic-cache timing requests until the LSQ-local fake DCache MainPipe reaches S2. StoreBuffer admission now only enters the fake pipe; the fake S2 callback performs the real sendTimingReq(), so StoreBuffer misses cannot allocate or merge MSHRs at fake-pipe admission time. Add StoreBuffer entry state for fake-pipe residency and S2 replay exits. Requests that fail fake S2 issue now leave the fake pipe, enter a replay queue, and retry from S0 later. Keep pre-admission blocking on the existing blocked entry path. Treat sending, in-mainpipe, and replay-queued entries as eviction-in-progress so younger same-line stores use a vice entry instead of mutating an eviction packet's payload. Keep StoreBuffer release on the existing cache response path. Validation: - git diff --check - scons build/RISCV/gem5.opt --gold-linker -j64 Change-Id: I2a8943c04ff2dc5f2f900f7727dec57685a6c8be
Change-Id: I4c9143524d76850db3cd1e6fa80f0861db4d73df
Send allocating L1D demand and prefetch read refills into the existing fake DCache mainpipe, while excluding permission-only and special whole-line write responses from refill modeling. Add counters to distinguish packet-LSQ refill notifications, owner-LSQ refill notifications, and skipped refill notifications without an LSQ target. Change-Id: Ib5ea665c71304390186d3b1ae5364997704f39e6
Change-Id: I4bedc68ed0bc83ed444852d33b4f59d506b4dd8e
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📝 WalkthroughWalkthroughThis PR adds a fake Dcache MainPipe model in LSQ for store-buffer eviction and refill flow, and connects BaseCache MSHR credit handling, refill notification, and prefetch gating to that model. ChangesLSQ MainPipe and store-buffer flow
BaseCache MainPipe integration
Sequence Diagram(s)sequenceDiagram
participant SbufferRequest
participant LSQ
participant BaseCache
participant MSHRQueue
SbufferRequest->>LSQ: sendPacketToCache()
LSQ->>LSQ: sbufferEnterDcacheMainPipe(pkt)
LSQ->>BaseCache: sendTimingReq(pkt)
BaseCache->>BaseCache: recvTimingResp()
BaseCache->>LSQ: notifyDcacheRefill(addr, need_data_read, on_complete)
BaseCache->>MSHRQueue: hold/release MainPipe credit
LSQ->>LSQ: retryReplayStoreBuffer()
Estimated code review effort🎯 5 (Critical) | ⏱️ ~120 minutes Possibly related PRs
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🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
✨ Finishing Touches📝 Generate docstrings
🧪 Generate unit tests (beta)
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happy-lx
reviewed
Jun 17, 2026
1. Model S3 as the tag write stage and keep S3 tag writes blocking S0 tag reads. 2. Model S4 as the data write stage and move fake mainpipe completion after S4 data write. 3. Move StoreBuffer cache request issue to fake S2 and let S2 misses exit the fake pipe instead of occupying S3/S4. 4. Release fake mainpipe MSHR credit no earlier than the next cache cycle. Change-Id: I3fb7b6bce803197d0427667ac2498a32b71b78de
🚀 Coremark Smoke Test Results
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happy-lx
previously approved these changes
Jun 18, 2026
1. Merge StoreBuffer same-set admission checks into the common blocked path to avoid overlapping early returns. 2. Release fake mainpipe MSHR credit at the S4 completion tick without adding another cache cycle. Change-Id: I49039d9c0a69a446a15c864dd7f2b3ddf78bdd4e
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happy-lx
previously approved these changes
Jun 22, 2026
Make load issue blocking observe whether the fake DCache mainpipe will have a refill tag write in S3 when the selected load reaches loadpipe S0. This keeps the issue-side block aligned with next-cycle loadpipe admission and avoids spurious refill S4 load bank conflicts caused by checking the current live S3 state. Change-Id: Id6a00ebbc7e1e530329c829052404cd92b04eec3
happy-lx
approved these changes
Jun 26, 2026
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Motivation
This PR adds a fake L1D DCache mainpipe model for timing and performance modeling.
In the current classic-cache path, L1D refill and StoreBuffer traffic can access cache resources without modeling the same mainpipe-side arbitration and resource conflicts as the hardware pipeline. This can make GEM5 underestimate contention from refill/store traffic, especially bank/data-array conflicts, same-set refill hazards, tag-write blocking, and StoreBuffer backpressure.
The fake mainpipe models these mainpipe-side timing constraints without turning the classic cache into a real mainpipe-based cache implementation. The goal is to improve performance modeling accuracy for L1D refill and StoreBuffer interactions.
Changes
Scope
This PR keeps the fake mainpipe as a performance model. It does not make the classic cache use a real DCache mainpipe for functional accesses.
The modeled request sources are currently L1D refill and StoreBuffer traffic.
Validation
The performance workflow is currently running at the time this PR description is prepared.
Summary by CodeRabbit
Release Notes
Refactor / New Features
Metrics
Cache Behavior