fix(axi_to_detailed_mem): operator precedence in per-bank read-error mask causes spurious SLVERR on multi-bank reads#426
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imchenwu merged 2 commits intoJun 22, 2026
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Operator precedence made the per-bank active-byte window wrong: 'addr % DataWidth/8' parses as '(addr % DataWidth)/8' and '... + 1<<size' as '(...+1)<<size'. A sub-word read could then count a bank it does not touch and raise a spurious SLVERR. Parenthesize both; error-free reads unaffected.
niwis
approved these changes
Jun 19, 2026
imchenwu
approved these changes
Jun 22, 2026
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Summary
In
axi_to_detailed_memthe per-bank read active-byte window uses two expressions that bind incorrectly under SystemVerilog operator precedence:meta_buf.addr % DataWidth/8parses as(meta_buf.addr % DataWidth) / 8, not the intended byte offsetmeta_buf.addr % (DataWidth/8).... + 1<<meta_buf.sizeparses as(... + 1) << meta_buf.size, not... + (1<<meta_buf.size).So
meta_buf_size_enable[i](the per-bank mask that gates read errors) is wrong. A sub-word read can count a bank it does not actually touch and raise a spuriousSLVERR(seen as a load-access-fault on the second beat of a multi-bank read into an uninitialised neighbour word).Fix
Parenthesize both sub-expressions so the window is
[off, off + (1<<size))withoff = addr % (DataWidth/8). Read-error masking only; error-free reads are unaffected. +0 area/latency.