axi_to_detailed_mem: Parenthesize read active-bank mask#427
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`meta_buf_size_enable` restricts the per-bank read-error reduction
(`resp_r_err = |(m2s_resp.err & meta_buf_size_enable)`) to the banks
actually covered by the access. Operator precedence broke its computation:
meta_buf.addr % DataWidth/8 parses as (meta_buf.addr % DataWidth) / 8
... + 1<<meta_buf.size parses as (... + 1) << meta_buf.size
instead of the intended `meta_buf.addr % (DataWidth/8)` and
`... + (1<<meta_buf.size)`.
The mask happens to be correct for beat-aligned reads but is wrong for
sub-beat address offsets. Example: a 4-byte read of the last 32-bit
register of a small register block over a 64-bit bus wrongly marks the
upper bank as active. An over-read of the adjacent unmapped word (as
emitted under devmode error reporting) then poisons the whole beat's
`r.resp` with SLVERR.
Parenthesize both sub-expressions: `% (DataWidth/8)` and `(1<<size)`.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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Just realised that this is a duplicate of #426. |
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Claudio and I stumbled across the following:
Problem
meta_buf_size_enablerestricts the per-bank read-error reduction (resp_r_err = |(m2s_resp.err & meta_buf_size_enable)) to the banks actually covered by the access. Operator precedence broke its computation:instead of the intended
meta_buf.addr % (DataWidth/8)and... + (1<<meta_buf.size).Impact
The mask happens to be correct for beat-aligned reads but is wrong for sub-beat address offsets. Example: a 4-byte read of the last 32-bit register of a small register block over a 64-bit bus wrongly marks the upper bank as active. An over-read of the adjacent unmapped word (as emitted under devmode error reporting) then poisons the whole beat's
r.respwith SLVERR.Fix
Parenthesize both sub-expressions:
% (DataWidth/8)and(1<<size).