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[PowerPC]Avoid combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSignExtendSetCC #199733

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[PowerPC]Avoid combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSignExtendSetCC #199733

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4645da5
fix combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSign…
diggerlin May 26, 2026
98a08b4
address comment
diggerlin Jun 10, 2026
647d6a4
add test case
diggerlin Jun 10, 2026
013bdf9
address comment
diggerlin Jun 11, 2026
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11 changes: 2 additions & 9 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16049,11 +16049,7 @@ static SDValue ConvertSETCCToXori(SDNode *N, SelectionDAG &DAG) {

SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
DAGCombinerInfo &DCI) const {
if (Subtarget.isISA3_1())
return SDValue();

EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
if (Subtarget.isISA3_1() || DCI.isBeforeLegalize())
return SDValue();

SDValue N0 = N->getOperand(0);
Expand All @@ -16073,16 +16069,12 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDValue X = isNullConstant(LHS) ? RHS : LHS;
EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.

if ((XVT == MVT::i64 || VT == MVT::i64) && !Subtarget.isPPC64())
return SDValue();

// On PPC64, i32 carry operations use the full 64-bit XER register,
// so we must use i64 operations to avoid incorrect results.
// Use i64 operations and truncate the result if needed.
if (XVT != MVT::i64 && Subtarget.isPPC64())
// Zero-extend if input type is not 64bits.
X = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, X);

EVT OpVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;

// Generate: SUBFE(ADDC(X, -1)).
Expand All @@ -16093,6 +16085,7 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDValue Sube = DAG.getNode(PPCISD::SUBE, dl, DAG.getVTList(OpVT, MVT::i32),
Addc, Addc, Carry);

EVT VT = N->getValueType(0);
// Truncate back to i32 if we used i64 operations.
if (OpVT == MVT::i64 && VT == MVT::i32)
return DAG.getNode(ISD::TRUNCATE, dl, VT, Sube);
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15 changes: 15 additions & 0 deletions llvm/test/CodeGen/PowerPC/issue-203012.ll
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@@ -0,0 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc-ibm-aix7.2.0.0 -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s

define i32 @main(i8 %0) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: clrlwi r3, r3, 24
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp2.not.i.4 = icmp eq i8 %0, 0
%1 = sext i1 %cmp2.not.i.4 to i32
ret i32 %1
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
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Expand Up @@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 56
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testComparesieqss.ll
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Expand Up @@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 48
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
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Expand Up @@ -100,14 +100,14 @@ define i64 @test_lleqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 56
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
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Expand Up @@ -99,14 +99,14 @@ define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 48
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
Expand Down