[PowerPC]Avoid combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSignExtendSetCC#199733
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diggerlin wants to merge 1 commit into
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[PowerPC]Avoid combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSignExtendSetCC#199733diggerlin wants to merge 1 commit into
diggerlin wants to merge 1 commit into
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@llvm/pr-subscribers-backend-powerpc Author: zhijian lin (diggerlin) Changessince ADDC only support 32bit and 64bit operand the patch avoid combine t13: i8,ch = load<(load (s8) from %ir.cond.i.i.i29.sroa.sel.sroa.sel.sroa.sel.sroa.sel, !tbaa <0x1112348b8>)> t0, t10, undef:i32 to t13: i8,ch = load<(load (s8) from %ir.cond.i.i.i29.sroa.sel.sroa.sel.sroa.sel.sroa.sel, !tbaa !8)> t0, t10, undef:i32 Full diff: https://github.com/llvm/llvm-project/pull/199733.diff 5 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 407093fd2b849..754b04e8c1049 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15873,7 +15873,7 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
return SDValue();
SDValue N0 = N->getOperand(0);
- if (N0.getOpcode() != ISD::SETCC)
+ if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse())
return SDValue();
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
@@ -15889,16 +15889,21 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDValue X = isNullConstant(LHS) ? RHS : LHS;
EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.
+ if (XVT != MVT::i32 && XVT != MVT::i64)
+ return SDValue();
+
if ((XVT == MVT::i64 || VT == MVT::i64) && !Subtarget.isPPC64())
return SDValue();
// On PPC64, i32 carry operations use the full 64-bit XER register,
// so we must use i64 operations to avoid incorrect results.
// Use i64 operations and truncate the result if needed.
- if (XVT != MVT::i64 && Subtarget.isPPC64())
+ if (XVT != MVT::i64 && Subtarget.isPPC64()) {
+ if (!X.hasOneUse())
+ return SDValue();
// Zero-extend if input type is not 64bits.
X = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, X);
-
+ }
EVT OpVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
// Generate: SUBFE(ADDC(X, -1)).
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
index 541aebb055347..094bbd458bedc 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
@@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 56
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 56
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
index 67e1729f2488e..eaf251077273e 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
@@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 48
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 48
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
index 75f3017ac0c4f..c920a64764f00 100644
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
@@ -100,14 +100,14 @@ define i64 @test_lleqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 56
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 56
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
index 0670168426a8a..84ef41ea2a817 100644
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
@@ -99,14 +99,14 @@ define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: clrldi r3, r3, 48
+; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: clrldi r3, r3, 48
+; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
|
Member
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What is the problem this PR is intended to address? The code in the description does not illustrate a bug - loads on PPC are extending, so the upper bits will be well defined. |
RolandF77
reviewed
May 29, 2026
Contributor
Author
without the patch, will combine to PPCISD::ADDC only support i32 and i64 , PPCISD::ADDC on i8 will hit assert. |
Contributor
Author
SelectionDAG::Combine-> PPCTargetLowering::PerformDAGCombine --> PPCTargetLowering::combineSignExtendSetCC and the SelectionDAG::Combine are run before the legalize types. will be lower to adding into will guarantee the optimization in PPCTargetLowering::combineSignExtendSetCC take effect after legalize types. |
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since ADDC only support 32bit and 64bit operand,
the patch avoid combine
to