feat(ci): add workflow dispatch for STA timing analysis CI by xiaokamikami · Pull Request #817 · OpenXiangShan/difftest

xiaokamikami · 2026-01-29T02:28:48Z

test

klin02 · 2026-01-29T08:32:48Z

+    # 12:00 UTC == 20:00 UTC+8
+    - cron: '00 12 * * *'
+  workflow_dispatch:
+  pull_request:


Remove it after test.

Emin017 · 2026-03-02T08:35:13Z

+
+# Set SDC file
+if [ -z "$SDC_FILE" ]; then
+    SDC_FILE="${YOSYS_STA_DIR}/scripts/default.sdc"


Note: The default SDC in yosys-sta may not be sufficient for complex processors like XiangShan. If we want a more accurate STA evaluation, we may need to add additional delay constraints on the input and output ports in the SDC.

We only want to conduct timing analysis on the modules on the diffftest side, in order to ensure that the difftest code can be synthesized on the FPGA.

klin02 · 2026-05-12T16:45:05Z

STA Timing Summary

Result: flow completed, setup violation found
Target: GatewayEndpoint, clock @ 500 MHz
Run: https://github.com/OpenXiangShan/difftest/actions/runs/25649104621/job/75283714301

Check	TNS	Worst Slack	Violations
Setup	-1.038	-0.149	1
Hold	0.000	0.057	0

Worst setup data path:

from: deltas_module.data_9_bits_value_20_4__reg_p:Q
to: batch_module.collector.in_valid_reg_p:D
main logic: deltas_module.splitters_0 / deltas_module.splitters_3
path delay: 2.109
required: 1.961
slack: -0.149
estimated frequency: 465.416 MHz

Worst clock-gating check:

endpoint: batch_module.collector.in_valid_reg_p_D_NOR2_X1_ZN_A2_NOR2_X1_A2_ZN_CLKGATE_X1_E:E
slack: -0.152

Worst hold path:

endpoint: batch_module.assembler.data_status_21_info_size_0__reg_p:D
slack: 0.057

Worst Setup Path Detail

| Point                                                                                                                                                   | Fanout | Capacitance | Resistance | Transition | Delta Delay | Incr   | Path   |
| clock (port)                                                                                                                                            |        | 2.744       | 0.000      | 0.000      |             | 0.000  | 0.000r |
| clock (clock net)                                                                                                                                       | 2002   |             |            |            | NA          |        |        |
| squashed_module.squashers_0.state_0_bits_valid_reg_p_QN_NOR3_X1_A1_A2_CLKGATE_X1_E:CK (CLKGATE_X1)                                                      |        | 0.002       | 0.000      | 0.000      |             | 0.000  | 0.000r |
| squashed_module.squashers_0.state_0_bits_valid_reg_p_QN_NOR3_X1_A1_A2_CLKGATE_X1_E:GCK (CLKGATE_X1)                                                     |        | 50.934      | 0.000      | 0.000      |             | 0.000  | 0.000r |
| deltas_module.data_0_valid_reg_p_CK (clock net)                                                                                                         | 53624  |             |            |            | NA          |        |        |
| deltas_module.data_9_bits_value_20_4__reg_p:CK (DFF_X1)                                                                                                 |        | 0.001       | 0.000      | 0.000      |             | 0.000  | 0.000r |
| clock core_clock (rise edge)                                                                                                                            |        |             |            |            |             | 0      | 0      |
| clock network delay (ideal)                                                                                                                             |        |             |            |            |             | 0.000  | 0.000  |
| deltas_module.data_9_bits_value_20_4__reg_p:CK (DFF_X1)                                                                                                 |        | 0.001       | 0.000      | 0.000      |             | 0.000  | 0.000r |
| deltas_module.data_9_bits_value_20_4__reg_p:Q (DFF_X1)                                                                                                  |        | 0.023       | 0.000      | 0.057      |             | 0.136  | 0.136r |
| deltas_module.data_9_bits_value_20_4_ (net)                                                                                                             | 14     |             |            |            | 0.000       |        |        |
| deltas_module.splitters_0.r_elems_20_4__reg_p_D_NOR2_X1_ZN_A2_INV_X1_ZN:A (INV_X1)                                                                      |        | 0.002       | 0.000      | 0.057      |             | 0.000  | 0.136r |
| deltas_module.splitters_0.r_elems_20_4__reg_p_D_NOR2_X1_ZN_A2_INV_X1_ZN:ZN (INV_X1)                                                                     |        | 0.014       | 0.000      | 0.025      |             | 0.039  | 0.175f |
| deltas_module.splitters_0.r_elems_20_4__reg_p_D_NOR2_X1_ZN_A2 (net)                                                                                     | 9      |             |            |            | 0.000       |        |        |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN_A3_OR4_X1_ZN_A3_OAI33_X1_ZN_B3_NAND3_X1_ZN:A2 (NAND3_X1) |        | 0.002       | 0.000      | 0.025      |             | 0.000  | 0.175f |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN_A3_OR4_X1_ZN_A3_OAI33_X1_ZN_B3_NAND3_X1_ZN:ZN (NAND3_X1) |        | 0.013       | 0.000      | 0.040      |             | 0.056  | 0.231r |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN_A3_OR4_X1_ZN_A3_OAI33_X1_ZN_B3 (net)                     | 8      |             |            |            | 0.000       |        |        |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN_A3_OR4_X1_ZN_A3_OAI33_X1_ZN:B3 (OAI33_X1)                |        | 0.002       | 0.000      | 0.040      |             | 0.000  | 0.231r |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN_A3_OR4_X1_ZN_A3_OAI33_X1_ZN:ZN (OAI33_X1)                |        | 0.001       | 0.000      | 0.014      |             | 0.033  | 0.265f |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN_A3_OR4_X1_ZN_A3 (net)                                    | 1      |             |            |            | 0.000       |        |        |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN_A3_OR4_X1_ZN:A3 (OR4_X1)                                 |        | 0.001       | 0.000      | 0.014      |             | 0.000  | 0.265f |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN:ZN (OR4_X1)                                 |        | 0.001       | 0.000      | 0.016      |             | 0.111  | 0.375f |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN:A3 (OR4_X1)                                              |        | 0.001       | 0.000      | 0.016      |             | 0.000  | 0.375f |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN_B1_OR4_X1_ZN:ZN (OR4_X1)                                              |        | 0.001       | 0.000      | 0.018      |             | 0.115  | 0.491f |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN:B1 (AOI21_X1)                                                         |        | 0.002       | 0.000      | 0.018      |             | 0.000  | 0.491f |
| deltas_module.splitters_3.first_updates_13_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_AOI21_X1_ZN:ZN (AOI21_X1)                                                         |        | 0.003       | 0.000      | 0.028      |             | 0.036  | 0.527r |
| deltas_module.splitters_3.first_updates_9_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_OAI222_X1_C1:B1 (OAI222_X1)                                                        |        | 0.002       | 0.000      | 0.028      |             | 0.000  | 0.527r |
| deltas_module.splitters_3.first_updates_9_NOR2_X1_ZN_A2_OR2_X1_ZN_A1_OAI222_X1_C1:ZN (OAI222_X1)                                                        |        | 0.002       | 0.000      | 0.022      |             | 0.039  | 0.565f |
| deltas_module.splitters_3.first_updates_11_NOR3_X1_ZN_A2_NOR2_X1_A1_ZN_NOR4_X1_A2:A4 (NOR4_X1)                                                          |        | 0.002       | 0.000      | 0.022      |             | 0.000  | 0.565f |
| deltas_module.splitters_3.first_updates_11_NOR3_X1_ZN_A2_NOR2_X1_A1_ZN_NOR4_X1_A2:ZN (NOR4_X1)                                                          |        | 0.003       | 0.000      | 0.064      |             | 0.108  | 0.673r |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_A1_AOI21_X1_ZN:B2 (AOI21_X1)                                                      |        | 0.002       | 0.000      | 0.064      |             | 0.000  | 0.673r |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_A1_AOI21_X1_ZN:ZN (AOI21_X1)                                                      |        | 0.001       | 0.000      | 0.017      |             | 0.019  | 0.692f |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2:A1 (OR3_X1)                                                                       |        | 0.001       | 0.000      | 0.017      |             | 0.000  | 0.692f |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2:ZN (OR3_X1)                                                                       |        | 0.003       | 0.000      | 0.016      |             | 0.074  | 0.766f |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_ZN_NOR4_X1_A4:A4 (NOR4_X1)                                                        |        | 0.002       | 0.000      | 0.016      |             | 0.000  | 0.766f |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_ZN_NOR4_X1_A4:ZN (NOR4_X1)                                                        |        | 0.001       | 0.000      | 0.036      |             | 0.073  | 0.839r |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_ZN_NOR4_X1_A4_ZN_AND4_X1_A2:A2 (AND4_X1)                                          |        | 0.001       | 0.000      | 0.036      |             | 0.000  | 0.839r |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_ZN_NOR4_X1_A4_ZN_AND4_X1_A2:ZN (AND4_X1)                                          |        | 0.001       | 0.000      | 0.010      |             | 0.060  | 0.899r |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_ZN_NOR4_X1_A4_ZN_AND4_X1_A2_ZN_BUF_X1_A:A (BUF_X1)                                |        | 0.001       | 0.000      | 0.010      |             | 0.000  | 0.899r |
| deltas_module.splitters_3.r_group_updates_27__AOI21_X1_B2_A_OR3_X1_A2_ZN_NOR4_X1_A4_ZN_AND4_X1_A2_ZN_BUF_X1_A:Z (BUF_X1)                                |        | 0.008       | 0.000      | 0.023      |             | 0.040  | 0.940r |

Full critical path summary

1. Timing Violation Summary (TNS)
--- TNS (Total Negative Slack) ---
| core_clock | max        | -1.038 |
| core_clock | min        | 0.000  |

2. Setup Critical Paths (Top 10)
--- Worst Setup Slack (Critical Paths) ---
| Endpoint                                                                           | Clock Group              | Delay Type | Path Delay | Path Required | CPPR  | Slack  | Freq(MHz) |
| batch_module.collector.in_valid_reg_p:D                                            | core_clock               | max        | 2.109f     | 1.961         | 0.000 | -0.149 | 465.416   |
| batch_module.collector.in_valid_reg_p:D                                            | core_clock               | max        | 2.109f     | 1.961         | 0.000 | -0.149 | 465.416   |
| batch_module._collector_out_bits_status_21_data_bytes_9__reg_p:D                   | core_clock               | max        | 2.071r     | 1.965         | 0.000 | -0.106 | 474.872   |
| batch_module._collector_out_bits_status_21_data_bytes_9__reg_p:D                   | core_clock               | max        | 2.071r     | 1.965         | 0.000 | -0.106 | 474.872   |
| batch_module.data_112_valid_reg_p:D                                                | core_clock               | max        | 2.062f     | 1.957         | 0.000 | -0.105 | 475.084   |
| batch_module.collector.in_valid_reg_p_D_NOR2_X1_ZN_A2_NOR2_X1_A2_ZN_CLKGATE_X1_E:E | **clock_gating_default** | max        | 2.107f     | 1.956         | 0.000 | -0.152 | NA        |
| batch_module.collector.in_valid_reg_p_D_NOR2_X1_ZN_A2_NOR2_X1_A2_ZN_CLKGATE_X1_E:E | **clock_gating_default** | max        | 1.869r     | 1.950         | 0.000 | 0.080  | NA        |
| _deltas_module_out_bits_58_valid_NOR2_X1_ZN_A1_NOR2_X1_A2_ZN_CLKGATE_X1_E:E        | **clock_gating_default** | max        | 1.492f     | 1.951         | 0.000 | 0.458  | NA        |
| deltas_module.splitters_5.first_updates_51_CLKGATE_X1_E:E                          | **clock_gating_default** | max        | 1.442f     | 1.950         | 0.000 | 0.508  | NA        |
| deltas_module.splitters_5.first_updates_119_CLKGATE_X1_E:E                         | **clock_gating_default** | max        | 1.442f     | 1.950         | 0.000 | 0.508  | NA        |

3. Hold Critical Paths (Top 10)
--- Worst Hold Slack (Critical Paths) ---
| batch_module.assembler.data_status_21_info_size_0__reg_p:D                         | core_clock               | min        | 0.063r     | 0.006         | 0.000 | 0.057  | NA        |
| batch_module.assembler.data_status_21_info_size_0__reg_p:D                         | core_clock               | min        | 0.063r     | 0.006         | 0.000 | 0.057  | NA        |
| batch_module.assembler.data_status_21_info_size_0__reg_p:D                         | core_clock               | min        | 0.064f     | 0.002         | 0.000 | 0.062  | NA        |
| batch_module.assembler.data_status_21_info_size_0__reg_p:D                         | core_clock               | min        | 0.064f     | 0.002         | 0.000 | 0.062  | NA        |
| batch_module.assembler._GEN_0_4__reg_p:D                                           | core_clock               | min        | 0.080f     | 0.002         | 0.000 | 0.078  | NA        |
| squashed_module.data_9_valid_INV_X1_A_ZN_OAI21_X1_B2_ZN_CLKGATE_X1_E:E             | **clock_gating_default** | min        | 0.124r     | -0.000        | 0.000 | 0.124  | NA        |
| squashed_module.data_21_valid_INV_X1_A_ZN_OAI21_X1_B2_ZN_CLKGATE_X1_E:E            | **clock_gating_default** | min        | 0.124r     | -0.000        | 0.000 | 0.124  | NA        |
| squashed_module.data_20_valid_INV_X1_A_ZN_OAI21_X1_B2_ZN_CLKGATE_X1_E:E            | **clock_gating_default** | min        | 0.124r     | -0.000        | 0.000 | 0.124  | NA        |
| squashed_module.data_13_valid_INV_X1_A_ZN_OAI21_X1_B2_ZN_CLKGATE_X1_E:E            | **clock_gating_default** | min        | 0.124r     | -0.000        | 0.000 | 0.124  | NA        |
| squashed_module.data_11_valid_INV_X1_A_ZN_OAI21_X1_B2_ZN_CLKGATE_X1_E:E            | **clock_gating_default** | min        | 0.124r     | -0.000        | 0.000 | 0.124  | NA        |

5. Path Statistics
Setup (max) path count: 11
Hold (min) path count: 11
Setup violation paths: 1
Hold timing met (no violations)

Note: this is RTL/gate-level STA without DEF/SPEF parasitics, so it should not be treated as congestion analysis.

xiaokamikami force-pushed the sta_ci branch 11 times, most recently from 388270b to 1f383f5 Compare January 29, 2026 08:29

klin02 reviewed Jan 29, 2026

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xiaokamikami force-pushed the sta_ci branch from 0701c6a to bb23d78 Compare February 25, 2026 03:24

Emin017 reviewed Mar 2, 2026

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xiaokamikami force-pushed the sta_ci branch 5 times, most recently from dde185c to 80545b2 Compare March 6, 2026 05:58

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xiaokamikami added 2 commits May 8, 2026 15:04

feat(ci): add workflow dispatch for STA timing analysis CI

d48a9d2

use node004

ce376fc

klin02 force-pushed the sta_ci branch 2 times, most recently from f6f4170 to 784d7be Compare May 8, 2026 18:18

klin02 added 2 commits May 9, 2026 02:18

modify xs generation and fix preprocess for new chisel

784d7be

STA: set YOSYS_SHARE default from aggressive to skip

9926a1b

ci: publish STA timing results

29114f6

xiaokamikami force-pushed the sta_ci branch from bd0818a to 29114f6 Compare May 13, 2026 02:58

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feat(ci): add workflow dispatch for STA timing analysis CI#817

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klin02 commented May 12, 2026

STA Timing Summary

Worst Setup Path Detail

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