modify xs generation and fix preprocess for new chisel

Author: klin02

.github/workflows/sta.yml

@@ -27,14 +27,14 @@ jobs:
       - name: Build XiangShan
         run: |
           cd $NOOP_HOME
-          make verilog DEBUG_ARGS="--difftest-config ESBIFDU --difftest-exclude Vec" FPGA=1 WITH_CHISELDB=0 WITH_CONSTANTIN=0 CONFIG=XSNoCDiffTopConfig -j10
+          make verilog CHISEL_TARGET=chirrtl DEBUG_ARGS="--difftest-config ESBIFDU" FPGA=1 WITH_CHISELDB=0 WITH_CONSTANTIN=0 CONFIG=FpgaDiffDefaultConfig -j64
 
       - name: Build DiffTest
         run: |
           cd $NOOP_HOME/difftest
           export NOOP_HOME=$(pwd)
-          make difftest_verilog PROFILE=../build/generated-src/difftest_profile.json NUMCORES=1 CONFIG=ESBIFDU  
-    
+          make difftest_verilog PROFILE=../build/generated-src/difftest_profile.json NUM_CORES=1 CONFIG=ESBIFDU -j64
+
       - name: Run STA
         run: |
           export PATH=/nfs/home/share/tools/yosys:$PATH

scripts/ieda/sv_preprocessor.py

@@ -20,12 +20,22 @@
 1. string type declarations - Comment out
 2. automatic keyword - Remove
 3. Assignment pattern syntax '{...} - Convert to compatible format
+4. procedural logic declaration initialization - Split declaration and assignment
 """
 
 import re
 import sys
 import os
 
+PROCEDURAL_START_RE = re.compile(r'^\s*(always(?:_\w+)?|initial|final)\b')
+LOGIC_INIT_DECL_RE = re.compile(
+    r'^(\s*)logic\s+'
+    r'((?:signed\s+)?(?:\[[^\]]+\]\s*)*)'
+    r'([A-Za-z_][A-Za-z0-9_$]*)'
+    r'(\s*(?:\[[^\]]+\]\s*)*)'
+    r'\s*=\s*(.*?);\s*(//.*)?$'
+)
+
 def preprocess_automatic_keyword(content):
     """
     Remove automatic keyword (not supported by Yosys)
@@ -42,6 +52,58 @@ def preprocess_automatic_keyword(content):
 
     return content
 
+def preprocess_procedural_logic_initialization(content):
+    """
+    Split initialized logic declarations inside procedural blocks.
+
+    Yosys accepts local declarations in procedural blocks, but rejects
+    declaration-time initialization there.
+
+    Original:
+      always_comb begin
+        logic tmp = in_valid & in_ready;
+      end
+
+    Converted:
+      always_comb begin
+        logic tmp;
+        tmp = in_valid & in_ready;
+      end
+    """
+    lines = content.splitlines()
+    result = []
+    procedural_depth = 0
+
+    def count_keyword(line, keyword):
+        code = line.split('//', 1)[0]
+        return len(re.findall(rf'\b{keyword}\b', code))
+
+    for line in lines:
+        in_procedural = procedural_depth > 0
+        match = LOGIC_INIT_DECL_RE.match(line) if in_procedural else None
+
+        if match:
+            indent, packed_dims, name, unpacked_dims, initializer, comment = match.groups()
+            packed_dims = ' '.join(packed_dims.split())
+            unpacked_dims = ''.join(unpacked_dims.split())
+            dims = f' {packed_dims}' if packed_dims else ''
+            comment = f' {comment}' if comment else ''
+            result.append(f"{indent}logic{dims} {name}{unpacked_dims};")
+            result.append(f"{indent}{name} = {initializer};{comment}")
+        else:
+            result.append(line)
+
+        begins = count_keyword(line, 'begin')
+        ends = count_keyword(line, 'end')
+        if PROCEDURAL_START_RE.match(line):
+            procedural_depth += max(begins - ends, 1)
+        elif procedural_depth > 0:
+            procedural_depth += begins - ends
+            if procedural_depth < 0:
+                procedural_depth = 0
+
+    return '\n'.join(result) + ('\n' if content.endswith('\n') else '')
+
 def preprocess_string_type(content):
     """
     Comment out string type declarations (not supported by Yosys)
@@ -137,6 +199,9 @@ def preprocess_file(input_file, output_file):
         # Remove automatic keyword
         content = preprocess_automatic_keyword(content)
 
+        # Split initialized procedural logic declarations
+        content = preprocess_procedural_logic_initialization(content)
+
         # Comment out string type declarations
         content = preprocess_string_type(content)