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Kunminghu v3 dcache dual port #6124

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50b5be0
feat(dcache): add one more dcache node
Ruomio Jun 20, 2026
4d4907e
fix(Config): set default param of numMemChannels as 1
Ruomio Jun 30, 2026
7dd5a19
bump(XSCache): update branch
Ruomio Jun 30, 2026
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2 changes: 1 addition & 1 deletion XSCache
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Submodule XSCache updated 7 files
+4 −1 src/main/scala/coupledL2/Common.scala
+97 −46 src/main/scala/coupledL2/CoupledL2.scala
+4 −1 src/main/scala/coupledL2/CustomL1Hint.scala
+3 −0 src/main/scala/coupledL2/L2Param.scala
+1 −3 src/main/scala/coupledL2/SourceB.scala
+4 −6 src/test/scala/TestTop_LLC.scala
+4 −4 src/test/scala/chi/TestTop.scala
5 changes: 3 additions & 2 deletions src/main/scala/top/Configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -272,7 +272,7 @@ class MinimalConfig(n: Int = 1) extends Config(
})
)

case class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => {
case class WithNKBL1D(n: Int, ways: Int = 8, numMemChannels: Int = 1) extends Config((site, here, up) => {
case XSTileKey =>
val sets = n * 1024 / ways / 64
up(XSTileKey).map(_.copy(
Expand All @@ -286,6 +286,7 @@ case class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) =>
nProbeEntries = 8,
nReleaseEntries = 18,
nMaxPrefetchEntry = 6,
numMemChannels = numMemChannels,
enableTagEcc = true,
enableDataEcc = true,
cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f))
Expand Down Expand Up @@ -533,7 +534,7 @@ class FuzzConfig(dummy: Int = 0) extends Config(
class DefaultConfig(n: Int = 1) extends Config(
OpenLLCConfig("16MB", ways = 16, banks = 4)
++ L2CacheConfig("2MB", inclusive = true, banks = 4, tp = false)
++ WithNKBL1D(64, ways = 4)
++ WithNKBL1D(64, ways = 4, numMemChannels = 2)
++ new BaseConfig(n)
)

Expand Down
12 changes: 10 additions & 2 deletions src/main/scala/xiangshan/L2Top.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -108,12 +108,20 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule

println(s"enableCHI: ${enableCHI}")
val l2cache = if (enableL2) {
val sliceCoherentClientMap =
if (coreParams.dcacheParametersOpt.exists(p => p.numMemChannels == 2 && p.channelSelByAddr) &&
coreParams.L2NBanks % 2 == 0) {
Some(Seq.tabulate(coreParams.L2NBanks)(i => i % 2))
} else {
None
}
val config = new Config((_, _, _) => {
case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
hartId = p(XSCoreParamsKey).HartId,
FPGAPlatform = debugOpts.FPGAPlatform,
hasMbist = hasMbist,
PrivateClintRange = if(UsePrivateClint) Some(TIMERRange) else None
PrivateClintRange = if(UsePrivateClint) Some(TIMERRange) else None,
sliceCoherentClientMap = sliceCoherentClientMap
)
case CHIIssue => p(CHIIssue)
case CHIAddrWidthKey => p(CHIAddrWidthKey)
Expand Down Expand Up @@ -223,7 +231,7 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
val pfCtrlFromCore = Input(new PrefetchCtrlFromCore)
val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
val l2_pmp_resp = Flipped(new PMPRespBundle)
val l2_hint = ValidIO(new L2ToL1Hint())
val l2_hint = Vec(numMemChannelsFromDcache, ValidIO(new L2ToL1Hint()))
val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
val l2_flush_en = Option.when(EnablePowerDown) (Input(Bool()))
val l2_flush_done = Option.when(EnablePowerDown) (Output(Bool()))
Expand Down
1 change: 1 addition & 0 deletions src/main/scala/xiangshan/Parameters.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -794,6 +794,7 @@ trait HasXSParameter {
def icacheCtrlAddress = coreParams.frontendParameters.icacheParameters.ctrlUnitParameters.Address // valid only when icacheCtrlEnabled is true

def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters())
def numMemChannelsFromDcache = coreParams.dcacheParametersOpt.map(_.numMemChannels).getOrElse(1)

// dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles
// for constrained LR/SC loop
Expand Down
6 changes: 2 additions & 4 deletions src/main/scala/xiangshan/XSCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
val l2PfCtrl = Output(new PrefetchCtrlFromCore)
val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
val beu_errors = Output(new XSL1BusErrors())
val l2_hint = Input(Valid(new L2ToL1Hint()))
val l2_hint = Input(Vec(numMemChannelsFromDcache, Valid(new L2ToL1Hint())))
val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2))
val l2_pmp_resp = new PMPRespBundle
val l2PfqBusy = Input(Bool())
Expand Down Expand Up @@ -220,11 +220,9 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException

memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw
memBlock.io.l2_hint.valid := io.l2_hint.valid
memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId
memBlock.io.l2_hint <> io.l2_hint
memBlock.io.l2_tlb_req <> io.l2_tlb_req
memBlock.io.l2_pmp_resp <> io.l2_pmp_resp
memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword
memBlock.io.l2PfqBusy := io.l2PfqBusy

// if l2 prefetcher use stream prefetch, it should be placed in XSCore
Expand Down
18 changes: 11 additions & 7 deletions src/main/scala/xiangshan/XSTile.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -59,9 +59,17 @@ class XSTile()(implicit p: Parameters) extends LazyModule

// =========== Components' Connection ============
// L1 to l1_xbar
coreParams.dcacheParametersOpt.map { _ =>
coreParams.dcacheParametersOpt.map { params =>
l2top.inner.misc_l2_pmu := l2top.inner.l1d_logger := memBlock.dcache_port :=
memBlock.l1d_to_l2_buffer.node := memBlock.dcache.clientNode

if (params.numMemChannels > 1 &&
memBlock.dcache_port_1.isDefined &&
memBlock.l1d_to_l2_buffer_1.isDefined &&
memBlock.dcache.clientNode_1.isDefined) {
l2top.inner.misc_l2_pmu := memBlock.dcache_port_1.get :=
memBlock.l1d_to_l2_buffer_1.get.node := memBlock.dcache.clientNode_1.get
}
}

l2top.inner.misc_l2_pmu := l2top.inner.l1i_logger := memBlock.frontendBridge.icache_node
Expand Down Expand Up @@ -180,9 +188,7 @@ class XSTile()(implicit p: Parameters) extends LazyModule
l2top.module.io.pfCtrlFromCore := core.module.io.l2PfCtrl

l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2)
core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId
core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword
core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid
core.module.io.l2_hint <> l2top.module.io.l2_hint

core.module.io.l2PfqBusy := false.B
core.module.io.debugTopDown.l2MissMatch := l2top.module.io.debugTopDown.l2MissMatch
Expand All @@ -196,9 +202,7 @@ class XSTile()(implicit p: Parameters) extends LazyModule
} else {

l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2)
core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId
core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword
core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid
core.module.io.l2_hint <> l2top.module.io.l2_hint

core.module.io.l2PfqBusy := false.B
core.module.io.debugTopDown.l2MissMatch := false.B
Expand Down
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