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fix(debug, csr): fix csr to support debug spec 1.0 #6104

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fix(debug, csr): fix csr to support debug spec 1.0 #6104

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6 changes: 3 additions & 3 deletions src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -57,9 +57,9 @@ class TrapEntryDEventModule(implicit val p: Parameters) extends Module with CSRE
private val satpFlushFirstFetchFault = in.satpFlushFirstFetchFault

private val hasExceptionInDmode = debugMode && hasTrap
val causeIntr = DcsrCause.Haltreq.asUInt
val causeExp = MuxCase(DcsrCause.None.asUInt, Seq(
val cause = MuxCase(DcsrCause.None.asUInt, Seq(
criticalErrorStateEnterDebug -> DcsrCause.Other.asUInt,
hasDebugIntr -> DcsrCause.Haltreq.asUInt,
triggerEnterDebugMode -> DcsrCause.Trigger.asUInt,
hasDebugEbreakException -> DcsrCause.Ebreak.asUInt,
hasSingleStep -> DcsrCause.Step.asUInt
Expand Down Expand Up @@ -92,7 +92,7 @@ class TrapEntryDEventModule(implicit val p: Parameters) extends Module with CSRE

out.dcsr.bits.V := current.privState.V.asUInt
out.dcsr.bits.PRV := current.privState.PRVM.asUInt
out.dcsr.bits.CAUSE := Mux(hasDebugIntr, causeIntr, causeExp)
out.dcsr.bits.CAUSE := cause
out.dpc.bits.epc := Mux(satpFlushFirstFetchFault, trapPC(63, 1), Mux(isFetchMalAddr, in.fetchMalTval(63, 1), trapPC(63, 1)))

out.targetPc.bits.pc := debugPc
Expand Down
13 changes: 8 additions & 5 deletions src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -57,9 +57,7 @@ trait DebugLevel { self: NewCSR =>
.setAddr(CSRs.tinfo)

val dcsr = Module(new CSRModule("Dcsr", new DcsrBundle) with TrapEntryDEventSinkBundle with DretEventSinkBundle with HasNmipBundle {
when(nmip){
reg.NMIP := nmip
}
regOut.NMIP := nmip
})
.setAddr(CSRs.dcsr)

Expand Down Expand Up @@ -292,12 +290,17 @@ class Tdata2Bundle extends CSRBundle {

// Tinfo
class TinfoBundle extends CSRBundle{
val VERSION = RO(31, 24).withReset(0.U)
.withDescription("Trigger-information format version field. XiangShan reports version 0, matching the Debug Spec 0.13-style encoding.")
val VERSION = TriggerVer(31, 24).withReset(TriggerVer.Spec_1dot0)
.withDescription("Trigger-information format version field. XiangShan reports version 1, matching the ratified Debug Spec 1.0 trigger encoding.")
val MCONTROL6EN = RO(6).withReset(1.U)
.withDescription("Indicates that the mcontrol6 trigger format is supported.")
}

object TriggerVer extends CSREnum with ROApply {
val Spec_2302 = Value(0.U)
val Spec_1dot0 = Value(1.U)
}

// Dscratch
class DscratchBundle extends OneFieldBundle(Some("Debug scratch register."))

Expand Down
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