Pair tage 2 taken - #830
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📝 WalkthroughWalkthroughAdds a new two-block PairTAGE BTB/TAGE predictor and integrates it into DecoupledBPUWithBTB; introduces TimedBaseBTBPredictor::refreshPredictionMeta, side-effect-free BTB lookup APIs and const-correct helpers across BTB predictors, extends FetchTarget with PairTAGE fields, and adds FTQ const accessors. Changes
Sequence Diagram(s)sequenceDiagram
participant Fetch as Fetch Unit
participant DBPU as DecoupledBPUWithBTB
participant PT as PairTAGE
participant FTQ as FetchTargetQueue
participant Hist as History Tracker
Fetch->>DBPU: request prediction(startPC, history)
DBPU->>PT: putPCHistory(startPC, history)
PT->>PT: TAGE lookup -> build first-block FullBTBPrediction
PT-->>DBPU: first-block FullBTBPrediction (pairtageUsed, pairPhase)
DBPU->>FTQ: enqueue first FetchTarget (pairPhase)
alt PairTAGE enabled && phase allowed && second-block candidate
DBPU->>PT: refreshPredictionMeta(secondStartPC, history, pred)
PT->>PT: lookupNoSideEffect -> second-block prediction/meta
PT-->>DBPU: second-block info (pairtageSecondBlock)
DBPU->>FTQ: conditionally enqueue second FetchTarget
end
Note over DBPU,PT: On resolution
DBPU->>PT: trainFromActualPred(firstFetchTarget, optionalSecondPred)
PT->>Hist: specUpdateHist / recoverHist / doUpdateHist
sequenceDiagram
participant Caller as DecoupledBPU
participant Predictor as BTB Predictor
participant NoSE as NoSideEffect Lookup
participant Meta as FullBTBPrediction
Caller->>Predictor: refreshPredictionMeta(startAddr, history, pred)
Predictor->>NoSE: lookupNoSideEffect(...) / processEntriesNoSideEffect(...)
NoSE->>NoSE: tag match, select entries (no MRU/LRU/stats changes)
NoSE-->>Meta: populate hit_entries / per-PC preds
Meta-->>Caller: refreshed prediction metadata snapshot
Estimated code review effort🎯 4 (Complex) | ⏱️ ~70 minutes Possibly related PRs
Suggested reviewers
🚥 Pre-merge checks | ✅ 3 | ❌ 2❌ Failed checks (1 warning, 1 inconclusive)
✅ Passed checks (3 passed)
✏️ Tip: You can configure your own custom pre-merge checks in the settings. ✨ Finishing Touches🧪 Generate unit tests (beta)
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🚀 Performance test triggered: gcc15-spec06-0.8c |
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🚀 Performance test triggered: gcc15-spec06-0.8c |
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🚀 Performance test triggered: gcc15-spec06-0.8c |
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🚀 Performance test triggered: gcc15-spec06-0.8c |
🚀 Coremark Smoke Test Results
✅ Difftest smoke test passed! |
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🚀 Performance test triggered: gcc15-spec06-0.8c |
🚀 Coremark Smoke Test Results
✅ Difftest smoke test passed! |
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🚀 Performance test triggered: gcc15-spec06-0.8c |
Change-Id: Ib4664b24db5194f524d7d5beb09f8749b4e6a9a6
Change-Id: I6d36ab621c338750f4a7ebd15ba0d5341e31c355
Change-Id: I736a2eba11bf8e5e297b572fb47335152eb50729
Change-Id: I7f9602e61370c328fc00e9f3f28ca2b7c9f718bb
Change-Id: I3fbbe413f46435d72dae908c6832089838669cd2
Change-Id: I20e915941b2765d3c6d5bff2a0fd7da6ff5d63e7
Change-Id: I75ff694758168a14fbb867a8028a8e965660f58f
The unit test and performance counters will be re-designed later. Change-Id: I129546906625411e7809085c440f7cbdb068aaad
Change-Id: Id554b8a3cfd9b0caa3b49d2345d458b24f8256a1
Remove dead pending second-block state, FetchTarget flags, duplicated PairTAGE metadata, no-op overrides, and unconsumed SimObject parameters. Keep prediction, training, history recovery, and two-fetch behavior unchanged. Test: scons build/RISCV/cpu/pred/btb/pairtage.o build/RISCV/cpu/pred/btb/decoupled_bpred.o build/RISCV/cpu/pred/btb/decoupled_bpred_stats.o -j64 Change-Id: I3f9efac3b170c63c9a86c4582ab9d1e1ea3320f0
Change-Id: I1d21a5b0d33fe7093b76d583d009ee4aabc6659e
Change-Id: I11730f645be338857e4d7b4aad9c31c205b59b3c
Change-Id: I1893c94e21729ca439a8a5007c252d0651bef7d5
Change-Id: I6c254a4c833acfea6ff3cc27ad11caa547a607ad
Change-Id: I62220194453b37e03767d99b7a60bf1eec56d02e
Change-Id: I0e250fb514463aa4efe41a41b98cb9b329758215
Change-Id: I8b9082e9f4d08bb79ce64894938908ffe6894af2
Change-Id: I3f6a4a10fba0839155e57ea0bc412c221d0e598d
Change-Id: I1fc0a8312f9e94d0c830139d41e4e537bdbfabeb
Change-Id: Ib6f8cf7c0acef0f7e3e7a5cffd8f565b2421170d
Change-Id: I81370bf4d9c16e652e0f4941ecd064b87a7cf11b
Change-Id: I7a970014cfdedefccc33fe4bde5a03c36da51459
Change-Id: Ibf1db7c1ec941eb633414feb91b552b084b14cff
RTL has a implemented 2 Fetch that only allow double fetch block in 64B. GEM5 will follow them later. Change-Id: Ic99921357c1da94809f3c00aa31a3832be1a9486
Change-Id: I9a35615c551f07e122f0b7f39befd01b3a18abd7
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No performance change in Aligned Evaluation (20.88 score per GHz) and SMT Evaluation (26.11 score per GHz) with commit 541137b as baseline. |
Change-Id: I1a04002d2cc77c621a8275b4cd74affc96b6b74f
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Summary by CodeRabbit
New Features
Improvements