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bpu,configs: Add optional BTBTAGE upper-bound mode for kmhv3 - #770

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jensen-yan merged 12 commits into
xs-devfrom
bigger-tage-align
Mar 16, 2026
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bpu,configs: Add optional BTBTAGE upper-bound mode for kmhv3#770
jensen-yan merged 12 commits into
xs-devfrom
bigger-tage-align

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@jensen-yan

@jensen-yan jensen-yan commented Mar 5, 2026

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Summary

  • add BTBTAGEUpperBound as an optional kmhv3 predictor mode
  • keep kmhv3 default predictor settings aligned with current xs-dev
  • reduce the configuration surface to a single --btb-tage-upper-bound switch
  • keep the upper-bound implementation using path-hash history when enabled

What changed

  • add the BTBTAGEUpperBound SimObject and implementation
  • wire it into kmhv3 so it replaces the default BTBTAGE only when the new flag is passed
  • merge with current xs-dev predictor changes, including the standalone MicroTAGE integration
  • add unit tests for exact-context lookup, allocation behavior, and path-hash history snapshots

Notes

  • default kmhv3 behavior remains unchanged unless --btb-tage-upper-bound is specified
  • this PR still keeps the supporting design docs and CI-analysis helper that were used during evaluation

Validation

  • python3 -m py_compile configs/common/xiangshan.py configs/example/kmhv3.py src/cpu/pred/BranchPredictor.py
  • scons build/RISCV/cpu/pred/btb/test/tage.test.debug --unit-test -j32
  • ./build/RISCV/cpu/pred/btb/test/tage.test.debug --gtest_filter=BTBTAGEUpperBoundTest.ExactContextLookup:BTBTAGEUpperBoundPathHashTest.PredictionUsesPathHashHistorySnapshot

Change-Id: I3a357ccab4ae078edb30bd4ffe5e01b5c6d9ac7f
Change-Id: I0e029d43a10487cc7090e15973db1fd84a731375
Change-Id: Ibdd30c6049dca43e022e5bd4e94a89e493397c33
Change-Id: If9f2e2a8099ac58c8f9ad5b86b00292eeebc48d4
Change-Id: I06630ca8db53f4fd944355fd03a166203c5dca11
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📝 Walkthrough

Walkthrough

Adds a new BTBTAGEUpperBound predictor (exact-history, path-hash option), registers it as a SimObject, wires a kmhv3 CLI flag to select it, updates BTBTAGE method signatures, adds tests, documentation, CI perf tooling, and build entries to include the new source.

Changes

Cohort / File(s) Summary
Config / CLI
configs/example/kmhv3.py, configs/common/xiangshan.py
Add --btb-tage-upper-bound CLI flag and conditional use of BTBTAGEUpperBound in kmhv3 config.
SimObject registration & build
src/cpu/pred/BranchPredictor.py, src/cpu/pred/SConscript
Register new BTBTAGEUpperBound SimObject type and add btb/btb_tage_ub.cc to build sources.
BTBTAGE core signature changes
src/cpu/pred/btb/btb_tage.hh, src/cpu/pred/btb/btb_tage.cc
Made getUseAltIdx(Addr) const, changed checkFoldedHist to virtual, and loosened UNIT_TEST access level to protected.
Upper-bound predictor implementation
src/cpu/pred/btb/btb_tage_ub.hh, src/cpu/pred/btb/btb_tage_ub.cc
Add full BTBTAGEUpperBound class: exact-history keyed tables, history-source enum (Outcome/PathHash), prediction/update/allocation flows, stats, and UNIT_TEST helpers.
Unit tests & test build
src/cpu/pred/btb/test/btb_tage.test.cc, src/cpu/pred/btb/test/SConscript
Add tests exercising BTBTAGEUpperBound behaviors and include new source in test SConscript.
Docs & research
docs/.../tage_index_capacity_exploration_20260305.md, docs/.../tage_upper_bound_design_20260310.md
Add research and design docs describing index-capacity exploration and UB-S(outcome) design.
CI / tooling
.codex/skills/ci-perf-analysis/*, .codex/skills/ci-perf-analysis/scripts/ci_perf_info.py
Add CI perf-analysis skill docs and a script to locate/print archived CI perf run scores.

Sequence Diagram(s)

sequenceDiagram
  rect rgba(200,200,255,0.5)
    participant FetchUnit
  end
  rect rgba(200,255,200,0.5)
    participant BTB
    participant BTB_TAGE
  end
  rect rgba(255,200,200,0.5)
    participant BTBTAGE_UB
    participant BasePredictor
  end

  FetchUnit->>BTB: request fetch target (startPC)
  BTB->>BTB_TAGE: lookup branch entry
  BTB_TAGE->>BTBTAGE_UB: query exact-history prediction (per-table index)
  BTBTAGE_UB-->>BTB_TAGE: prediction + meta (main/alt)
  BTB_TAGE->>BasePredictor: consult base predictor if UB miss
  BasePredictor-->>BTB_TAGE: base prediction
  BTB_TAGE-->>FetchUnit: final prediction(s) with metadata
  FetchUnit->>BTBTAGE_UB: on resolution -> update()/allocate() (history snapshot)
Loading

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~45 minutes

Possibly related PRs

Suggested labels

perf, align-kmhv3

Suggested reviewers

  • Yakkhini
  • CJ362ff

Poem

🐇 I nibble histories, hash each hop,
exact paths stored where entries crop.
Tables whisper indices, allocs take flight,
an upper-bound predictor hops into light.
Hop—predict, update, then sleep till night.

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 4.17% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (2 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The title accurately describes the main change: adding an optional upper-bound mode variant of BTBTAGE for the kmhv3 configuration, which is the primary focus across the modified files.

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Comment thread configs/example/kmhv3.py Outdated

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🧹 Nitpick comments (1)
configs/example/kmhv3.py (1)

115-120: Consider removing redundant MGSC table configuration.

These MGSC table enable/disable settings have no effect since mgsc.enabled = False on line 111. You may want to remove them to reduce configuration clutter, or keep them if they serve as documentation for future reference.

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@configs/example/kmhv3.py` around lines 115 - 120, The MGSC table
enable/disable lines (cpu.branchPred.mgsc.enableBwTable, enableLTable,
enableITable, enableGTable, enablePTable, enableBiasTable) are redundant because
cpu.branchPred.mgsc.enabled is set to False; remove these per-table settings to
reduce clutter, or alternatively leave a single commented note documenting the
intended defaults if you want them for future reference—either delete the six
cpu.branchPred.mgsc.enable* lines or replace them with a one-line comment
referencing mgsc.enabled and the intended table defaults.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.

Nitpick comments:
In `@configs/example/kmhv3.py`:
- Around line 115-120: The MGSC table enable/disable lines
(cpu.branchPred.mgsc.enableBwTable, enableLTable, enableITable, enableGTable,
enablePTable, enableBiasTable) are redundant because cpu.branchPred.mgsc.enabled
is set to False; remove these per-table settings to reduce clutter, or
alternatively leave a single commented note documenting the intended defaults if
you want them for future reference—either delete the six
cpu.branchPred.mgsc.enable* lines or replace them with a one-line comment
referencing mgsc.enabled and the intended table defaults.

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: e4592414-45b1-43ab-88f9-7e915039121a

📥 Commits

Reviewing files that changed from the base of the PR and between 318c57c and b44d5b1.

📒 Files selected for processing (4)
  • configs/example/kmhv3.py
  • src/cpu/pred/BranchPredictor.py
  • src/cpu/pred/btb/btb_tage.cc
  • src/cpu/pred/btb/btb_tage.hh

Change-Id: Ib8b67365d8196e4b2ec0044a8883e6983b88b2f6
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🚀 Coremark Smoke Test Results

Branch IPC Change
Base (xs-dev) 2.2203 -
This PR 2.2679 📈 +0.0476 (+2.14%)

✅ Difftest smoke test passed!

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Actionable comments posted: 1

🧹 Nitpick comments (4)
docs/Gem5_Docs/frontend/tage_index_capacity_exploration_20260305.md (3)

107-117: Commit-chain section may go stale; link to immutable PR artifacts.

The hardcoded short-hash list is useful now but brittle over time. Consider adding direct links to the PR commits (or a permalinked range) so readers can always resolve the exact history.

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@docs/Gem5_Docs/frontend/tage_index_capacity_exploration_20260305.md` around
lines 107 - 117, The commit list under the section "7. 当前分支提交链(CI触发)" is
brittle; replace the hardcoded short-hash entries for branch `bigger-tage-align`
with immutable links (full commit SHAs or permalink URLs) pointing to each
commit or a single permalinked range/PR so readers can always resolve history;
update the five listed items (including the one mentioning `tableSizes`) to use
their respective commit URLs or the PR permalink and leave the descriptive text
unchanged.

85-94: Prefer a compact table with relative deltas.

For quick comparison, present off/mix2/mix4/mix8 as a table and include % deltas vs off for both IPC and mispred. This will make trend strength and tradeoffs much clearer.

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@docs/Gem5_Docs/frontend/tage_index_capacity_exploration_20260305.md` around
lines 85 - 94, Replace the current bullet lists for gobmk and sjeng with a
compact table for each benchmark (or a single combined table) that lists the
metrics IPC and mispred as rows and columns for off, mix2, mix4, mix8, plus
additional columns showing the percent delta vs off for each mix (e.g., "mix2
Δ%" = (mix2 - off)/off * 100). Keep the original numeric values (IPC: 2.544804,
2.580220, 2.583373, 2.580409; mispred: 44249, 42602, 42686, 42887 for gobmk; and
IPC: 2.116851, 2.120000, 2.129908, 2.124130; mispred: 47856, 47515, 47429, 47691
for sjeng), format them into columns Off / Mix2 / Mix4 / Mix8 and append
percent-change columns for each mix relative to Off so readers can quickly see
trend strength and tradeoffs.

22-30: Add full reproducibility metadata for the reported numbers.

The setup/results sections still miss key replay inputs (exact command line, checkpoint ID/path, random seed policy, binary/input identifiers). Please add them so others can reproduce the 5M-window IPC/mispred numbers exactly.

Also applies to: 83-94

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@docs/Gem5_Docs/frontend/tage_index_capacity_exploration_20260305.md` around
lines 22 - 30, The docs are missing full reproducibility metadata for the
reported 5M-window IPC/mispred numbers; update the setup/results sections to
include the exact gem5 command line used (including --maxinsts=5000000
--warmup-insts-no-switch=0 and any other flags), the exact checkpoint identifier
or path and how it was created, the random seed policy (seed value or how seeds
were chosen), and precise binary/input identifiers for each reported slice
(e.g., gobmk_nngs_18098, sjeng_84999) plus any config toggles used
(system.cpu[0].branchPred.mgsc.enabled and
system.cpu[0].branchPred.tage.enableBankConflict); apply the same additions to
the other occurrence mentioned (lines 83-94) so anyone can reproduce the
IPC/mispred values exactly.
src/cpu/pred/btb/btb_tage.cc (1)

87-90: Consider normalizing indexMixTables against numPredictors.

If configured larger than numPredictors, behavior silently becomes “mix all tables”. Clamping (or warning) would make config intent clearer.

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@src/cpu/pred/btb/btb_tage.cc` around lines 87 - 90, Clamp or validate the
indexMixTables value against numPredictors to prevent silent “mix all tables”
behavior: in the constructor (where indexMixTables is initialized) or
immediately after configuration, check if indexMixTables > numPredictors and
either set indexMixTables = numPredictors (clamp) or log a warning and adjust
accordingly; reference the members indexMixTables and numPredictors and update
any code that reads indexMixTables so it uses the validated/clamped value.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.

Inline comments:
In `@src/cpu/pred/btb/btb_tage.cc`:
- Around line 217-224: The bank-conflict bookkeeping must use the same PC used
for index calculation (the derived indexPc/baseIndexPc) instead of always using
startPC; update the bank-tracking logic that runs alongside the predictor loop
(when enableBankConflict is true) to compute bank/index IDs from indexPc (or
baseIndexPc) the same way getTageIndex uses it so conflict/defer decisions match
the selected indexed PC; locate where bank bookkeeping references startPC and
replace it to derive bank indices from indexPc (or reuse baseIndexPc) consistent
with buildIndexPC/useBranchPcForIndex and the loop over i, and ensure predMeta
paths (indexFoldedHist) are still honored.

---

Nitpick comments:
In `@docs/Gem5_Docs/frontend/tage_index_capacity_exploration_20260305.md`:
- Around line 107-117: The commit list under the section "7. 当前分支提交链(CI触发)" is
brittle; replace the hardcoded short-hash entries for branch `bigger-tage-align`
with immutable links (full commit SHAs or permalink URLs) pointing to each
commit or a single permalinked range/PR so readers can always resolve history;
update the five listed items (including the one mentioning `tableSizes`) to use
their respective commit URLs or the PR permalink and leave the descriptive text
unchanged.
- Around line 85-94: Replace the current bullet lists for gobmk and sjeng with a
compact table for each benchmark (or a single combined table) that lists the
metrics IPC and mispred as rows and columns for off, mix2, mix4, mix8, plus
additional columns showing the percent delta vs off for each mix (e.g., "mix2
Δ%" = (mix2 - off)/off * 100). Keep the original numeric values (IPC: 2.544804,
2.580220, 2.583373, 2.580409; mispred: 44249, 42602, 42686, 42887 for gobmk; and
IPC: 2.116851, 2.120000, 2.129908, 2.124130; mispred: 47856, 47515, 47429, 47691
for sjeng), format them into columns Off / Mix2 / Mix4 / Mix8 and append
percent-change columns for each mix relative to Off so readers can quickly see
trend strength and tradeoffs.
- Around line 22-30: The docs are missing full reproducibility metadata for the
reported 5M-window IPC/mispred numbers; update the setup/results sections to
include the exact gem5 command line used (including --maxinsts=5000000
--warmup-insts-no-switch=0 and any other flags), the exact checkpoint identifier
or path and how it was created, the random seed policy (seed value or how seeds
were chosen), and precise binary/input identifiers for each reported slice
(e.g., gobmk_nngs_18098, sjeng_84999) plus any config toggles used
(system.cpu[0].branchPred.mgsc.enabled and
system.cpu[0].branchPred.tage.enableBankConflict); apply the same additions to
the other occurrence mentioned (lines 83-94) so anyone can reproduce the
IPC/mispred values exactly.

In `@src/cpu/pred/btb/btb_tage.cc`:
- Around line 87-90: Clamp or validate the indexMixTables value against
numPredictors to prevent silent “mix all tables” behavior: in the constructor
(where indexMixTables is initialized) or immediately after configuration, check
if indexMixTables > numPredictors and either set indexMixTables = numPredictors
(clamp) or log a warning and adjust accordingly; reference the members
indexMixTables and numPredictors and update any code that reads indexMixTables
so it uses the validated/clamped value.

ℹ️ Review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 2636f8a7-bf63-429d-946f-21ef7bd864f3

📥 Commits

Reviewing files that changed from the base of the PR and between b44d5b1 and 9774e83.

📒 Files selected for processing (5)
  • configs/example/kmhv3.py
  • docs/Gem5_Docs/frontend/tage_index_capacity_exploration_20260305.md
  • src/cpu/pred/BranchPredictor.py
  • src/cpu/pred/btb/btb_tage.cc
  • src/cpu/pred/btb/btb_tage.hh
🚧 Files skipped from review as they are similar to previous changes (1)
  • configs/example/kmhv3.py

Comment thread src/cpu/pred/btb/btb_tage.cc Outdated
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🚀 Coremark Smoke Test Results

Branch IPC Change
Base (xs-dev) 2.2203 -
This PR 2.2328 📈 +0.0125 (+0.56%)

✅ Difftest smoke test passed!

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[Generated by GEM5 Performance Robot]
commit: 9774e83
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

PR Master Diff(%)
Score 17.72 17.84 -0.70 🔴

[Generated by GEM5 Performance Robot]
commit: 9774e83
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

PR Previous Commit Diff(%)
Score 17.72 17.92 -1.14 🔴

Change-Id: If39f7384f40450cae4c7dbb285bc8ea71ef0486b
Change-Id: I8ccbe4c2e97c9e87274dabc61f41b4d4398b79d0
Change-Id: I6d73773fcaa021a7d2a0e7c45eb5f9d61aeddda5
@XiangShanRobot

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[Generated by GEM5 Performance Robot]
commit: c69f618
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

PR Previous Commit Diff(%)
Score 18.26 17.92 +1.85 🟢

Add a path-hash-backed exact-history mode to BTBTAGEUpperBound.
This keeps the UB implementation aligned with the current RTL-friendly PHR
semantics and exposes a kmhv3 flag for direct comparison against UB-S.

Change-Id: I9bb7832a5770833562a48dcf7116d55ef8db8b15
Make kmhv3 default to the UB-P path-hash mode when BTBTAGEUpperBound is enabled, and keep an explicit flag to fall back to outcome-history mode for comparisons.

Change-Id: I98cade975baa98cbddfde28bda281cc97b384ec6

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Actionable comments posted: 2

🧹 Nitpick comments (2)
src/cpu/pred/btb/test/btb_tage.test.cc (1)

1018-1059: Avoid pinning these history tests to table 0.

Both tests are validating history/meta behavior, but they currently fail if allocation lands anywhere other than table 0. That couples them to the current allocation policy instead of the behavior under test.

♻️ Suggested test hardening
+    auto hasExactEntryInAnyTable =
+        [&](Addr pc, const boost::dynamic_bitset<> &hist) {
+            for (int t = 0; t < tage->numPredictors; ++t) {
+                if (tage->hasExactEntry(t, pc, hist)) {
+                    return true;
+                }
+            }
+            return false;
+        };
+
     EXPECT_TRUE(tage->hasExactEntry(0, entry.pc, historyA));
     EXPECT_FALSE(tage->hasExactEntry(0, entry.pc, historyB));
+    EXPECT_TRUE(hasExactEntryInAnyTable(entry.pc, historyA));
+    EXPECT_FALSE(hasExactEntryInAnyTable(entry.pc, historyB));
@@
-    EXPECT_TRUE(tage->hasExactEntry(0, newEntry.pc, historyA));
+    EXPECT_TRUE(hasExactEntryInAnyTable(newEntry.pc, historyA));
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@src/cpu/pred/btb/test/btb_tage.test.cc` around lines 1018 - 1059, The tests
assume allocation always lands in table 0 by calling hasExactEntry(0, ...);
instead make the assertion table-index agnostic by checking for the exact entry
across all TAGE tables (e.g., loop i from 0 to tage->numTables()-1 or use an
existing finder API) and assert that at least one table contains the entry;
update both tests (the one after update/recoverHist and the new
conditional-entry test that calls putPCHistory/update) to replace the fixed
hasExactEntry(0, ...) checks with a scan over all tables (using
tage->numTables() or the equivalent method) or a helper like findExactEntry(...)
so the test validates history/meta behavior regardless of which table allocation
chooses.
.codex/skills/ci-perf-analysis/scripts/ci_perf_info.py (1)

36-50: Iterate through jobs to find archive source instead of assuming first job.

This code currently assumes the first job returned by GitHub is the archive-producing job. While this is correct for the current workflow structure (which has a single job), it's fragile. If the workflow later adds setup/post jobs, enables matrix fan-out, or reorders jobs, this code will break. Scanning all run jobs until finding one whose logs contain ARCHIVE_RE makes the archive lookup resilient to workflow changes.

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In @.codex/skills/ci-perf-analysis/scripts/ci_perf_info.py around lines 36 - 50,
Change the brittle single-job assumption by returning all job ids and scanning
each job's logs until ARCHIVE_RE is found: modify get_job_id to return a list of
job ids (e.g., rename to get_job_ids and return [str(job["id"]) for job in
data.get("jobs", [])]), then update get_archive_path to accept a run_id (or call
get_job_ids) and iterate over those job ids, calling
run_cmd(["gh","api",f"repos/{REPO}/actions/jobs/{job_id}/logs"]) for each and
returning match.group(1) for the first job whose logs match ARCHIVE_RE; raise
the existing SystemExit if no job contains the archive.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.

Inline comments:
In @.codex/skills/ci-perf-analysis/SKILL.md:
- Around line 43-49: Fix the shell export example: replace the incorrect
assignment that expands the variable name (`export $GEM5_DATA_PROC_HOME=xxx`)
with a proper export/assignment for GEM5_DATA_PROC_HOME (e.g., use export
GEM5_DATA_PROC_HOME=xxx or assign then export GEM5_DATA_PROC_HOME) so the
environment variable GEM5_DATA_PROC_HOME is actually set as intended in
SKILL.md.

---

Nitpick comments:
In @.codex/skills/ci-perf-analysis/scripts/ci_perf_info.py:
- Around line 36-50: Change the brittle single-job assumption by returning all
job ids and scanning each job's logs until ARCHIVE_RE is found: modify
get_job_id to return a list of job ids (e.g., rename to get_job_ids and return
[str(job["id"]) for job in data.get("jobs", [])]), then update get_archive_path
to accept a run_id (or call get_job_ids) and iterate over those job ids, calling
run_cmd(["gh","api",f"repos/{REPO}/actions/jobs/{job_id}/logs"]) for each and
returning match.group(1) for the first job whose logs match ARCHIVE_RE; raise
the existing SystemExit if no job contains the archive.

In `@src/cpu/pred/btb/test/btb_tage.test.cc`:
- Around line 1018-1059: The tests assume allocation always lands in table 0 by
calling hasExactEntry(0, ...); instead make the assertion table-index agnostic
by checking for the exact entry across all TAGE tables (e.g., loop i from 0 to
tage->numTables()-1 or use an existing finder API) and assert that at least one
table contains the entry; update both tests (the one after update/recoverHist
and the new conditional-entry test that calls putPCHistory/update) to replace
the fixed hasExactEntry(0, ...) checks with a scan over all tables (using
tage->numTables() or the equivalent method) or a helper like findExactEntry(...)
so the test validates history/meta behavior regardless of which table allocation
chooses.

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  • .codex/skills/ci-perf-analysis/SKILL.md
  • .codex/skills/ci-perf-analysis/scripts/ci_perf_info.py
  • configs/common/xiangshan.py
  • configs/example/kmhv3.py
  • docs/Gem5_Docs/frontend/tage_index_capacity_exploration_20260305.md
  • docs/Gem5_Docs/frontend/tage_upper_bound_design_20260310.md
  • src/cpu/pred/BranchPredictor.py
  • src/cpu/pred/SConscript
  • src/cpu/pred/btb/btb_tage.cc
  • src/cpu/pred/btb/btb_tage.hh
  • src/cpu/pred/btb/btb_tage_ub.cc
  • src/cpu/pred/btb/btb_tage_ub.hh
  • src/cpu/pred/btb/test/SConscript
  • src/cpu/pred/btb/test/btb_tage.test.cc
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  • src/cpu/pred/btb/btb_tage.cc
  • src/cpu/pred/btb/btb_tage.hh

Comment thread .codex/skills/ci-perf-analysis/SKILL.md
Comment thread src/cpu/pred/btb/btb_tage_ub.cc

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🧹 Nitpick comments (1)
configs/example/kmhv3.py (1)

118-128: MGSC disabled; downstream table configs are now no-ops.

With mgsc.enabled = False, the MGSC component's isEnabled() returns false and putPCHistory() returns early (per src/cpu/pred/btb/btb_mgsc.cc:513), bypassing all prediction logic. This makes the table configuration on lines 122-127 (enableBwTable, enableLTable, etc.) effectively dead code.

If this is intentional (preserving config for future re-enablement), consider adding a brief comment. Otherwise, these lines could be removed or wrapped in a conditional to improve clarity.

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@configs/example/kmhv3.py` around lines 118 - 128, The MGSC config sets
cpu.branchPred.mgsc.enabled = False which makes MGSC.isEnabled() false and
causes putPCHistory() to return early, rendering downstream flags
(cpu.branchPred.mgsc.enableBwTable, enableLTable, enableITable, enableGTable,
enablePTable, enableBiasTable) no-ops; either remove these dead flag lines or
wrap them in a conditional that only sets them when cpu.branchPred.mgsc.enabled
is True, or add a concise inline comment explaining they are intentionally
preserved for future re-enablement so readers know the redundancy is deliberate
(reference symbols: cpu.branchPred.mgsc.enabled, MGSC.isEnabled(),
putPCHistory(), and the enable* table flags).
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.

Nitpick comments:
In `@configs/example/kmhv3.py`:
- Around line 118-128: The MGSC config sets cpu.branchPred.mgsc.enabled = False
which makes MGSC.isEnabled() false and causes putPCHistory() to return early,
rendering downstream flags (cpu.branchPred.mgsc.enableBwTable, enableLTable,
enableITable, enableGTable, enablePTable, enableBiasTable) no-ops; either remove
these dead flag lines or wrap them in a conditional that only sets them when
cpu.branchPred.mgsc.enabled is True, or add a concise inline comment explaining
they are intentionally preserved for future re-enablement so readers know the
redundancy is deliberate (reference symbols: cpu.branchPred.mgsc.enabled,
MGSC.isEnabled(), putPCHistory(), and the enable* table flags).

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  • configs/common/xiangshan.py
  • configs/example/kmhv3.py

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[Generated by GEM5 Performance Robot]
commit: 705affd
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

PR Previous Commit Diff(%)
Score 18.23 18.26 -0.15 🔴

@jensen-yan jensen-yan changed the title Bigger tage align bpu,configs: Add optional BTBTAGE upper-bound mode for kmhv3 Mar 13, 2026
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🚀 Coremark Smoke Test Results

Branch IPC Change
Base (xs-dev) 2.2665 -
This PR 2.2665 ➡️ 0.0000 (0.00%)

✅ Difftest smoke test passed!

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[Generated by GEM5 Performance Robot]
commit: f95abde
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

PR Master Diff(%)
Score 18.27 18.27 0.00

[Generated by GEM5 Performance Robot]
commit: f95abde
workflow: gem5 Align BTB Performance Test(0.3c)

Align BTB Performance

Overall Score

PR Previous Commit Diff(%)
Score 18.27 18.23 +0.23 🟢

@jensen-yan
jensen-yan merged commit 6cc70c4 into xs-dev Mar 16, 2026
3 checks passed
@jensen-yan
jensen-yan deleted the bigger-tage-align branch March 16, 2026 07:40
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4 participants