PCC and DDC refactor#40
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This removes the fesvr and spike dependencies (and means that running the simulator doesn't disable terminal echo)
This is not supported by the version of the Sail model we are testing against
This includes removing some workarounds that modified the core in RVFI_DII mode to align with Sail with compressed instructions disabled
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Seems to take a chunk out of area: 30% CHERI overhead instead of 37% on LUTs, 15% instead of 19% on FFs. Only trouble is it has made timing a little worse (FMax of 38MHz vs 41MHz), so we should probably have a look at that before this gets merged! |
Delay issuing to backend until any change of PCC bounds has committed
…rly for CSR update interlocking.
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This depends on our previous two PRs and replaces the "remove PCC" commit.
Fixes #39
I'm about to measure area and see how much difference it makes!