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New DRC check: flag overlapping copper pours on different nets

Status: Open.

#189 In tscircuit/checks;

· zkasuran opened on Aug 8, 2026

SMT pads and plated holes are not checked against min_board_edge_clearance

Status: Open.

#187 In tscircuit/checks;

· zkasuran opened on Aug 8, 2026

checkCourtyardOverlap silently ignores polygon and pill courtyards

Status: Open.

#185 In tscircuit/checks;

· zkasuran opened on Aug 8, 2026

Different-net vias with overlapping copper pass DRC (only the drill hole is measured)

Status: Open.

#183 In tscircuit/checks;

· zkasuran opened on Aug 8, 2026

checkTracesAreContiguous accepts a trace endpoint connected to a pad on a different layer

Status: Open.

#167 In tscircuit/checks;

· abdalraof-albarbar opened on Jul 2, 2026

New DRC Check: Check vias aren't too close to pads

good first issueGood for newcomersGood for newcomers

major

Status: Open.

#44 In tscircuit/checks;

· seveibar opened on May 14, 2025

Dependency Dashboard

Status: Open.

#20 In tscircuit/checks;

· renovate opened on Mar 24, 2025

Add all the Design Rule Checks for JLCPCB

Status: Open.

#15 In tscircuit/checks;

· seveibar opened on Sep 17, 2024

Check for pcb_trace intersections when determining if two pcb_traces are connected

Status: Open.

#14 In tscircuit/checks;

· seveibar opened on Sep 14, 2024