Add Sipeed SLogic Analyzer Driver Support by taonyx · Pull Request #275 · sigrokproject/libsigrok

Commits on Dec 17, 2025

sipeed-slogic-analyzer: Initial driver skeleton.
taonyx
committed
protocol: Adjust transfer duration and tolerance settings for improved performance
taonyx
committed
protocol: Refactor slogic_model structure for improved clarity and const correctness
taonyx
committed
protocol: Update SLogic 16U3 sample rates and limits for accuracy
taonyx
committed
protocol: Update voltage threshold for improved accuracy in scan function
taonyx
committed
protocol: Update SLogic 16U3 sample rates and voltage threshold for accuracy
taonyx
committed
protocol: Fix condition (wait for trigger) for sample acquisition in receive_transfer function
taonyx
committed
fix: ensure data are fully handled before be triggered
taonyx
committed
fix: drop 2 samples for hardware BUG and ensure pre_samples to be sent
taonyx
committed
fix: Update limit sample rates for SLogic 16U3 based on platform
taonyx
committed
fix: Update sample drop size for hardware bug workaround
taonyx
committed
std: add std_i32_idx()

Mixaill
authored and
taonyx
committed
sipeed-slogic-analyzer: fix missing function return value

Mixaill
authored and
taonyx
committed
sipeed-slogic-analyzer: rename pattern modes

Mixaill
authored and
taonyx
committed
sipeed-slogic-analyzer: fix initial threshold voltage value

Mixaill
authored and
taonyx
committed
sipeed-slogic-analyzer: update sampling channels based on current ones

Mixaill
authored and
taonyx
committed
sipeed-slogic-analyzer: switch from SR_CONF_BUFFERSIZE to SR_CONF_NUM_LOGIC_CHANNELS

Mixaill
authored and
taonyx
committed
sipeed-slogic-analyzer: fix timeout judgement, use expected rate for timeout calculation in data transfer
taonyx
committed
Merge pull request #2 from taorye/slogic-dev
taonyx
authored

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Add Sipeed SLogic Analyzer Driver Support - #275

Add Sipeed SLogic Analyzer Driver Support#275
taonyx wants to merge 25 commits into
sigrokproject:masterfrom
sipeed:slogic-dev

Commits on Dec 17, 2025

sipeed-slogic-analyzer: Initial driver skeleton.

protocol: Adjust transfer duration and tolerance settings for improved performance

protocol: Refactor slogic_model structure for improved clarity and const correctness

protocol: Update SLogic 16U3 sample rates and limits for accuracy

protocol: Update voltage threshold for improved accuracy in scan function

protocol: Update SLogic 16U3 sample rates and voltage threshold for accuracy

protocol: Fix condition (wait for trigger) for sample acquisition in receive_transfer function

fix: ensure data are fully handled before be triggered

fix: drop 2 samples for hardware BUG and ensure pre_samples to be sent

fix: Update limit sample rates for SLogic 16U3 based on platform

fix: Update sample drop size for hardware bug workaround

std: add std_i32_idx()

sipeed-slogic-analyzer: fix missing function return value

sipeed-slogic-analyzer: rename pattern modes

sipeed-slogic-analyzer: fix initial threshold voltage value

sipeed-slogic-analyzer: update sampling channels based on current ones

sipeed-slogic-analyzer: switch from SR_CONF_BUFFERSIZE to SR_CONF_NUM_LOGIC_CHANNELS

sipeed-slogic-analyzer: fix timeout judgement, use expected rate for timeout calculation in data transfer

Merge pull request #2 from taorye/slogic-dev

Commits on Feb 26, 2026

fix: SWIG 4.4+ compatibility

ci: update PKGBUILD for Arch AUR

Commits on Mar 3, 2026

Merge pull request #3 from aisuneko/slogic-dev

Commits on Jul 13, 2026

sipeed-slogic-analyzer: add support for SLogic32U3 with samplerate and channel configurations

sipeed-slogic-analyzer: fix model check and update bitwise operations for sample channels

Commits on Jul 24, 2026

sipeed-slogic-analyzer: fix premature transfer timeout