Skip to content
Draft
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions src/cheri/contributors.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ This RISC-V specification has been contributed to directly or indirectly by:
* Maja Malenko <maja.malenko@codasip.com>
* A. Theodore Markettos <theo.markettos@cl.cam.ac.uk>
* Alfredo Mazzinghi <alfredo.mazzinghi@cl.cam.ac.uk>
* Jan Matyas <jan.matyas@codasip.com>
* Dave McEwan <dave.mcewan@codasip.com>
* David McKay <david.mckay@codasip.com>
* Jamie Melling <jamie.melling@codasip.com>
Expand Down
30 changes: 27 additions & 3 deletions src/cheri/debug-integration.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,9 @@ relaxed if some other means of accessing capabilities in integer registers,
such as an extension of the Access Register abstract command, is added.

The following sequences demonstrate how a debugger can read and write a capability
in `{creg}1` if `MXLEN` is 64, `hartinfo.dataaccess` is 0, `hartinfo.dataaddr` is
0xBF0, `hartinfo.datasize` is 1, `hartinfo.nscratch` is at least 1, `dmstatus.impebreak` is 0,
and `abstractcs.progbufsize` is 5:
in `{creg}1` using the program buffer if `MXLEN` is 64, `hartinfo.dataaccess` is 0,
`hartinfo.dataaddr` is 0xBF0, `hartinfo.datasize` is 1, `hartinfo.nscratch` is at least 1,
`dmstatus.impebreak` is 0, and `abstractcs.progbufsize` is 5:

[source,subs=attributes+]
----
Expand Down Expand Up @@ -85,6 +85,30 @@ no way to discover the former property.
setting `transfer` to 1 and `write` to 0).
====

==== Abstract Commands

This section describes the behavior of _Abstract Commands_, specified by the
_RISC-V Debug Specification_ in section 3.7, on harts that implement
{cheri_base_ext_name}.

===== Access Register Abstract Command

TODO

// This section should be created per the outcome of:
// https://github.com/riscv/riscv-cheri/issues/1039

===== Access Memory Abstract Command

If the debug module implements _Access Memory Abstract Command_, then any write
to memory through this abstract command shall clear the capability tag (or tags)
associated with that memory location.

[NOTE]
====
Misaligned write may clear at most two capability tags.
====

==== Debug Mode

When executing code due to an abstract command, the hart stays in debug mode
Expand Down
Loading