Add multicast support to XBAR

.ci/Memora.yml

@@ -328,5 +328,23 @@ artifacts:
       - src/axi_xbar_unmuxed.sv
       - src/axi_xbar.sv
       - test/tb_axi_xbar.sv
+      - test/tb_axi_xbar_pkg.sv
     outputs:
       - build/axi_xbar-%.tested
+
+  axi_mcast_xbar-%:
+    inputs:
+      - Bender.yml
+      - include
+      - scripts/run_vsim.sh
+      - src/axi_pkg.sv
+      - src/axi_intf.sv
+      - src/axi_test.sv
+      - src/axi_mcast_demux.sv
+      - src/axi_err_slv.sv
+      - src/axi_mcast_mux.sv
+      - src/axi_mcast_xbar.sv
+      - test/tb_axi_mcast_xbar.sv
+      - test/tb_axi_xbar_pkg.sv
+    outputs:
+      - build/axi_mcast_xbar-%.tested

.github/workflows/gitlab-ci.yml

@@ -9,7 +9,7 @@ on:
 jobs:
   gitlab-ci:
     runs-on: ubuntu-latest
-    timeout-minutes: 310
+    timeout-minutes: 360
     steps:
       - name: Check Gitlab CI
         uses: pulp-platform/pulp-actions/gitlab-ci@v2

.gitlab-ci.yml

@@ -188,3 +188,10 @@ axi_xbar:
   <<: *run_vsim
   variables:
     TEST_MODULE: axi_xbar
+  timeout: 6h 00m
+
+axi_mcast_xbar:
+  <<: *run_vsim
+  variables:
+    TEST_MODULE: axi_mcast_xbar
+  timeout: 6h 00m

Bender.yml

@@ -5,6 +5,7 @@ package:
     - "Thomas Benz <tbenz@iis.ee.ethz.ch>" # current maintainer
     - "Michael Rogenmoser <michaero@iis.ee.ethz.ch>" # current maintainer
     - "Matheus Cavalcante <matheusd@iis.ee.ethz.ch>"
+    - "Luca Colagrande <colluca@iis.ee.ethz.ch>"
     - "Tim Fischer <fischeti@iis.ee.ethz.ch>"
     - "Noah Huetter <huettern@ethz.ch>"
     - "Cyril Koenig <cykoenig@iis.ee.ethz.ch>"
@@ -18,10 +19,13 @@ package:
     - "Nils Wistoff <nwistoff@iis.ee.ethz.ch>"
     - "Florian Zaruba <zarubaf@iis.ee.ethz.ch>"
 
+remotes:
+  pulp: https://github.com/pulp-platform
+
 dependencies:
-  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 }
-  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.5 }
-  tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 }
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: v2-dev }
+  common_verification: 0.2.5
+  tech_cells_generic: 0.2.2
 
 export_include_dirs:
   - include
@@ -37,22 +41,16 @@ sources:
   - src/axi_intf.sv
   # Level 2
   - src/axi_atop_filter.sv
-  - src/axi_burst_splitter_gran.sv
-  - src/axi_burst_unwrap.sv
   - src/axi_bus_compare.sv
   - src/axi_cdc_dst.sv
   - src/axi_cdc_src.sv
   - src/axi_cut.sv
   - src/axi_delayer.sv
-  - src/axi_demux_simple.sv
-  - src/axi_dw_downsizer.sv
-  - src/axi_dw_upsizer.sv
   - src/axi_fifo.sv
   - src/axi_fifo_delay_dyn.sv
   - src/axi_id_remap.sv
   - src/axi_id_prepend.sv
   - src/axi_inval_filter.sv
-  - src/axi_isolate.sv
   - src/axi_join.sv
   - src/axi_lite_demux.sv
   - src/axi_lite_dw_converter.sv
@@ -64,38 +62,50 @@ sources:
   - src/axi_lite_regs.sv
   - src/axi_lite_to_apb.sv
   - src/axi_lite_to_axi.sv
+  - src/axi_mcast_demux_simple.sv
+  - src/axi_mcast_mux.sv
   - src/axi_modify_address.sv
-  - src/axi_mux.sv
   - src/axi_rw_join.sv
   - src/axi_rw_split.sv
   - src/axi_serializer.sv
   - src/axi_slave_compare.sv
   - src/axi_throttle.sv
   - src/axi_to_detailed_mem.sv
   # Level 3
-  - src/axi_burst_splitter.sv
   - src/axi_cdc.sv
-  - src/axi_demux.sv
+  - src/axi_demux_simple.sv
   - src/axi_err_slv.sv
-  - src/axi_dw_converter.sv
   - src/axi_from_mem.sv
-  - src/axi_id_serialize.sv
-  - src/axi_lfsr.sv
+  - src/axi_mcast_demux_mapped.sv
   - src/axi_multicut.sv
-  - src/axi_to_axi_lite.sv
+  - src/axi_mux.sv
   - src/axi_to_mem.sv
   - src/axi_zero_mem.sv
   # Level 4
-  - src/axi_interleaved_xbar.sv
-  - src/axi_iw_converter.sv
+  - src/axi_burst_splitter_gran.sv
+  - src/axi_demux.sv
   - src/axi_lite_xbar.sv
-  - src/axi_xbar_unmuxed.sv
-  - src/axi_to_mem_banked.sv
+  - src/axi_mcast_xbar_unmuxed.sv
   - src/axi_to_mem_interleaved.sv
   - src/axi_to_mem_split.sv
   # Level 5
-  - src/axi_xbar.sv
+  - src/axi_burst_splitter.sv
+  - src/axi_burst_unwrap.sv
+  - src/axi_dw_downsizer.sv
+  - src/axi_dw_upsizer.sv
+  - src/axi_id_serialize.sv
+  - src/axi_interleaved_xbar.sv
+  - src/axi_isolate.sv
+  - src/axi_mcast_xbar.sv
+  - src/axi_to_mem_banked.sv
+  - src/axi_xbar_unmuxed.sv
   # Level 6
+  - src/axi_dw_converter.sv
+  - src/axi_iw_converter.sv
+  - src/axi_to_axi_lite.sv
+  - src/axi_xbar.sv
+  # Level 7
+  - src/axi_lfsr.sv
   - src/axi_xp.sv
 
   - target: synth_test
@@ -131,6 +141,7 @@ sources:
       - test/tb_axi_lite_to_apb.sv
       - test/tb_axi_lite_to_axi.sv
       - test/tb_axi_lite_xbar.sv
+      - test/tb_axi_mcast_xbar.sv
       - test/tb_axi_modify_address.sv
       - test/tb_axi_serializer.sv
       - test/tb_axi_sim_mem.sv

doc/axi_demux.md

@@ -45,7 +45,6 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple
 |:----------------------------------|:------------|
 | `clk_i`                           | Clock to which all other signals (except `rst_ni`) are synchronous. |
 | `rst_ni`                          | Reset, asynchronous, active-low. |
-| `test_i`                          | Test mode enable (active-high). |
 | `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. |
 | `slv_{aw,ar}_select_i`            | Index of the master port to which a write or read, respectively, is demultiplexed.  This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). |
 | `mst_*`                           | Array of master ports of the demultiplexer.  The array index of each port is the index of the master port. |
@@ -71,7 +70,7 @@ Setting the `UniqueIds` parameter to `1'b1` reduces the area complexity of the d
 
 `2 * 2^AxiLookBits` counters track the number of [in-flight](../doc#in-flight) transactions.  That is, for each ID in the (potentially) reduced set of IDs of `AxiLookBits` bits, there is one counter for write transactions and one for read transactions.  Each counter can count up to (and including) `MaxTrans`, and there is a register that holds the index of the master port to which a counter is assigned.
 
-When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID.  If the indexed counter has a value greater than zero and its master port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another master port.  The demultiplexer then stalls the AW or AR.  In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the master port index of the counter.  A counter is decremented upon a handshake a B respectively last R beat at a slave port.
+When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID.  If the indexed counter has a value greater than zero and its master port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another master port.  The demultiplexer then stalls the AW or AR.  In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the master port index of the counter.  A counter associated with the AW or AR channel is decremented upon a handshake on the slave port respectively on the B channel or on the R channel in correspondence of the last beat.
 
 W beats are routed to the master port defined by the value of `slv_aw_select_i` for the corresponding AW.  As the order of the W bursts is given by the order of the AWs, the select signals are stored in a FIFO queue.  This FIFO is pushed upon a handshake on the AW slave channel and popped upon a handshake of the last W beat of a burst on a W master channel.
 

doc/axi_lite_demux.md

@@ -38,7 +38,6 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple
 |:----------------------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
 | `clk_i`                           | Clock to which all other signals (except `rst_ni`) are synchronous.                                                                                                                              |
 | `rst_ni`                          | Reset, asynchronous, active-low.                                                                                                                                                                 |
-| `test_i`                          | Test mode enable (active-high).                                                                                                                                                                  |
 | `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer.                                                                                                                                                          |
 | `slv_{aw,ar}_select_i`            | Index of the master port to which a write or read, respectively, is demultiplexed.  This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). |
 | `mst_*`                           | Array of master ports of the demultiplexer.  The array index of each port is the index of the master port.                                                                                       |

doc/axi_lite_mailbox.md

@@ -27,7 +27,6 @@ This table describes the ports of the module.
 |:---------------|:---------------------------|:-------------------------------------------------------|
 | `clk_i`        | `input  logic`             | clock                                                  |
 | `rst_ni`       | `input  logic`             | asynchronous reset active low                          |
-| `test_i`       | `input  logic`             | testmode enable                                        |
 | `slv_reqs_i`   | `input  req_lite_t  [1:0]` | requests of the two AXI4-Lite ports                    |
 | `slv_resps_o`  | `output resp_lite_t [1:0]` | responses of the two AXI4-Lite ports                   |
 | `irq_o`        | `output logic       [1:0]` | interrupt output for each port                         |

doc/axi_lite_xbar.md

@@ -55,7 +55,6 @@ If two crossbars are connected in both directions, meaning both have one of thei
 |:------------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
 | `clk_i`                 | Clock to which all other signals (except `rst_ni`) are synchronous.                                                                                                           |
 | `rst_ni`                | Reset, asynchronous, active-low.                                                                                                                                              |
-| `test_i`                | Test mode enable (active-high).                                                                                                                                               |
 | `slv_ports_*`           | Array of slave ports of the crossbar.  The array index of each port is the index of the slave port.  This index will be prepended to all requests at one of the master ports. |
 | `mst_ports_*`           | Array of master ports of the crossbar.  The array index of each port is the index of the master port.                                                                         |
 | `addr_map_i`            | Address map of the crossbar (see section *Address Map* above).                                                                                                                |

doc/axi_mux.md

@@ -4,7 +4,7 @@ The opposite function to the AXI demultiplexer is performed by the AXI Multiplex
 
 ![Block-diagram of the AXI 4 Multiplexer Module.](axi_mux.png  "Block-diagram of the AXI 4 Multiplexer Module.")
 
-The Multiplexer module is has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which slave port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with:
+The Multiplexer module has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which slave port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with:
 
 ```systemverilog
 $clog2(NoSlavePorts)

doc/axi_xbar.md

@@ -5,7 +5,7 @@
 
 ## Design Overview
 
-`axi_xbar` is a fully-connected crossbar, which means that each master module that is connected to a *slave port* for of the crossbar has direct wires to all slave modules that are connected to the *master ports* of the crossbar.
+`axi_xbar` is a fully-connected crossbar, which means that each master module that is connected to a *slave port* of the crossbar has direct wires to all slave modules that are connected to the *master ports* of the crossbar.
 A block-diagram of the crossbar is shown below:
 
 ![Block-diagram showing the design of the full AXI4 Crossbar.](axi_xbar.png  "Block-diagram showing the design of the full AXI4 Crossbar.")
@@ -49,7 +49,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
 | `LatencyMode`        | `enum logic [9:0]` | Latency on the individual channels, defined in detail in section *Pipelining and Latency* below. |
 | `AxiIdWidthSlvPorts` | `int unsigned`     | The AXI ID width of the slave ports. |
 | `AxiIdUsedSlvPorts`  | `int unsigned`     | The number of slave port ID bits (starting at the least significant) the crossbar uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below).  This value has to be less or equal than `AxiIdWidthSlvPorts`. |
-| `UniqueIds`          | `bit`              | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar.  See the [`axi_demux` documentation](axi_demux#ordering-and-stalls) for details. |
+| `UniqueIds`          | `bit`              | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar.  See the [`axi_demux` documentation](axi_demux.md#ordering-and-stalls) for details. |
 | `AxiAddrWidth`       | `int unsigned`     | The AXI address width. |
 | `AxiDataWidth`       | `int unsigned`     | The AXI data width. |
 | `NoAddrRules`        | `int unsigned`     | The number of address map rules. |
@@ -71,7 +71,6 @@ If two crossbars are connected in both directions, meaning both have one of thei
 |:------------------------|:------------|
 | `clk_i`                 | Clock to which all other signals (except `rst_ni`) are synchronous. |
 | `rst_ni`                | Reset, asynchronous, active-low. |
-| `test_i`                | Test mode enable (active-high). |
 | `slv_ports_*`           | Array of slave ports of the crossbar.  The array index of each port is the index of the slave port.  This index will be prepended to all requests at one of the master ports. |
 | `mst_ports_*`           | Array of master ports of the crossbar.  The array index of each port is the index of the master port. |
 | `addr_map_i`            | Address map of the crossbar (see section *Address Map* above). |

scripts/axi_intercon_gen.py

@@ -150,7 +150,6 @@ def assigns(w, max_idw, masters, slaves):
 def instance_ports(w, id_width, masters, slaves):
     ports = [Port('clk_i'  , 'clk_i'),
              Port('rst_ni', 'rst_ni'),
-             Port('test_i', "1'b0"),
              Port('slv_ports_req_i' , 'masters_req'),
              Port('slv_ports_resp_o', 'masters_resp'),
              Port('mst_ports_req_o' , 'slaves_req'),

scripts/run_vsim.sh

@@ -219,7 +219,7 @@ exec_test() {
                             MST_ID=5
                             for DATA_WIDTH in 64 256; do
                                 for PIPE in 0 1; do
-                                    call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \
+                                    call_vsim tb_axi_xbar -t 1ns      \
                                         -gTbNumMasters=$NUM_MST       \
                                         -gTbNumSlaves=$NUM_SLV        \
                                         -gTbAxiIdWidthMasters=$MST_ID \
@@ -241,6 +241,32 @@ exec_test() {
                 done
             done
             ;;
+        axi_mcast_xbar)
+            for GEN_ATOP in 0 1; do
+                for NUM_MST in 1 6; do
+                    for NUM_SLV in 2 9; do
+                        for MST_ID_USE in 3 5; do
+                            MST_ID=5
+                            for DATA_WIDTH in 64 256; do
+                                for PIPE in 0; do
+                                    for UNIQUE_IDS in 0; do
+                                        call_vsim tb_axi_mcast_xbar -t 1ns \
+                                            -gTbNumMasters=$NUM_MST        \
+                                            -gTbNumMcastSlaves=$NUM_SLV    \
+                                            -gTbAxiIdWidthMasters=$MST_ID  \
+                                            -gTbAxiIdUsed=$MST_ID_USE      \
+                                            -gTbAxiDataWidth=$DATA_WIDTH   \
+                                            -gTbPipeline=$PIPE             \
+                                            -gTbEnAtop=$GEN_ATOP           \
+                                            -gTbUniqueIds=$UNIQUE_IDS
+                                    done
+                                done
+                            done
+                        done
+                    done
+                done
+            done
+            ;;
         *)
             call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx"
             ;;

src/axi_atop_filter.sv

@@ -345,13 +345,12 @@ module axi_atop_filter #(
     end
   end
 
-  stream_register #(
-    .T(r_resp_cmd_t)
+  cc_stream_register #(
+    .data_t(r_resp_cmd_t)
   ) r_resp_cmd (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (1'b0),
-    .testmode_i (1'b0),
     .valid_i    (r_resp_cmd_push_valid),
     .ready_o    (r_resp_cmd_push_ready),
     .data_i     (r_resp_cmd_push),