Implement support for TP-Link M7350 V3 (MDM9625)

lk2nd/device/2nd/rules.mk

@@ -63,6 +63,7 @@ $(OUTBOOTIMG): $(OUTBINDTB) $(OUTQCDT) $(RAMDISK)
 		--kernel=$< \
 		--output=$@ \
 		--cmdline="$(MKBOOTIMG_CMDLINE)" \
+		--tags_offset 0x06500000 \
 		$(if $(OUTQCDT),--qcdt=$(OUTQCDT)) \
 		$(if $(MKBOOTIMG_BASE),--base=$(MKBOOTIMG_BASE)) \
 		$(if $(MKBOOTIMG_PAGESIZE),--pagesize=$(MKBOOTIMG_PAGESIZE)) \

lk2nd/device/dts/mdm9625/msm9625-v2.1-mtp.dts

@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include <skeleton64.dtsi>
+#include <lk2nd.dtsi>
+
+/ {
+	qcom,msm-id = <134 7 0x20001>, <152 7 0x20001>, <149 7 0x20001>,
+		      <150 7 0x20001>, <151 7 0x20001>, <148 7 0x20001>,
+		      <173 7 0x20001>, <174 7 0x20001>, <175 7 0x20001>;
+};
+
+&lk2nd {
+	tp-link-m7350-v3 {
+		model = "TP-Link M7350";
+		compatible = "tplink,m7350-v3";
+
+		gpio-keys {
+			compatible = "gpio-keys";
+
+			menu {
+				lk2nd,code = <KEY_HOME>;
+				gpios = <&tlmm 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			};
+
+			reset {
+				lk2nd,code = <KEY_HOME>;
+				gpios = <&tlmm 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			};
+		};
+	};
+};

lk2nd/device/dts/mdm9625/rules.mk

@@ -0,0 +1,4 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+QCDTBS += \
+	$(LOCAL_DIR)/msm9625-v2.1-mtp.dtb

lk2nd/fastboot/rules.mk

@@ -3,7 +3,6 @@ LOCAL_DIR := $(GET_LOCAL_DIR)
 
 OBJS += \
 	$(LOCAL_DIR)/fetch.o \
-	$(LOCAL_DIR)/hash.o \
 	$(LOCAL_DIR)/misc.o \
 
 ifneq ($(filter DISPLAY_SPLASH_SCREEN=1,$(DEFINES)),)

platform/mdm9x25/acpuclock.c

@@ -30,6 +30,7 @@
 #include <assert.h>
 #include <debug.h>
 #include <reg.h>
+#include <mmc.h>
 #include <clock.h>
 #include <platform/clock.h>
 #include <platform/iomap.h>
@@ -84,20 +85,87 @@ void clock_config_uart_dm(uint8_t id)
 	int ret;
 	char clk_name[64];
 
-    ret = clk_get_set_enable("uart_iface_clk", 0, 1);
-    if (ret)
+	ret = clk_get_set_enable("uart_iface_clk", 0, 1);
+	if (ret)
 	{
 		dprintf(CRITICAL, "failed to set uart_iface_clk ret = %d\n", ret);
 		ASSERT(0);
 	}
 
 	snprintf(clk_name, 64, "uart%u_core_clk", id);
 
-    ret = clk_get_set_enable(clk_name, 7372800, 1);
+	ret = clk_get_set_enable(clk_name, 7372800, 1);
 	if (ret)
 	{
 		dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
 		ASSERT(0);
 	}
 }
 
+void clock_init_mmc(uint32_t interface)
+{
+	char clk_name[64];
+	int ret;
+
+	snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
+
+	/* enable interface clock */
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if (ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+	int ret;
+	char clk_name[64];
+
+	snprintf(clk_name, 64, "sdc%u_core_clk", interface);
+
+	/* Disalbe MCI_CLK before changing the sdcc clock */
+#ifndef MMC_SDHCI_SUPPORT
+	mmc_boot_mci_clk_disable();
+#endif
+
+	if (freq == MMC_CLK_400KHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 400000, 1);
+	}
+	else if (freq == MMC_CLK_25MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 25000000, 1);
+	}
+	else if (freq == MMC_CLK_50MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 50000000, 1);
+	}
+	else if (freq == MMC_CLK_96MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 100000000, 1);
+	}
+	else if (freq == MMC_CLK_200MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 200000000, 1);
+	}
+	else
+	{
+		dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+		ASSERT(0);
+		return;
+	}
+
+	if (ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
+		ASSERT(0);
+	}
+
+	/* Enalbe MCI clock */
+#ifndef MMC_SDHCI_SUPPORT
+	mmc_boot_mci_clk_enable();
+#endif
+}

platform/mdm9x25/include/platform/clock.h

@@ -31,7 +31,10 @@
 
 #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
 
+void platform_clock_init(void);
 void hsusb_clock_init(void);
 void clock_config_uart_dm(uint8_t id);
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
 
 #endif

platform/mdm9x25/include/platform/iomap.h

@@ -124,4 +124,26 @@
 #define USB_HS_SYSTEM_CMD_RCGR               (CLK_CTL_BASE + 0x490)
 #define USB_HS_SYSTEM_CFG_RCGR               (CLK_CTL_BASE + 0x494)
 
+/* SDCC2 */
+#define SDCC2_BCR                   (CLK_CTL_BASE + 0x500) /* block reset */
+#define SDCC2_APPS_CBCR             (CLK_CTL_BASE + 0x504) /* branch control */
+#define SDCC2_AHB_CBCR              (CLK_CTL_BASE + 0x508)
+#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
+#define SDCC2_CMD_RCGR              (CLK_CTL_BASE + 0x510) /* cmd */
+#define SDCC2_CFG_RCGR              (CLK_CTL_BASE + 0x514) /* cfg */
+#define SDCC2_M                     (CLK_CTL_BASE + 0x518) /* m */
+#define SDCC2_N                     (CLK_CTL_BASE + 0x51C) /* n */
+#define SDCC2_D                     (CLK_CTL_BASE + 0x520) /* d */
+
+/* SDCC3 */
+#define SDCC3_BCR                   (CLK_CTL_BASE + 0x540) /* block reset */
+#define SDCC3_APPS_CBCR             (CLK_CTL_BASE + 0x544) /* branch control */
+#define SDCC3_AHB_CBCR              (CLK_CTL_BASE + 0x548)
+#define SDCC3_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x54C)
+#define SDCC3_CMD_RCGR              (CLK_CTL_BASE + 0x550) /* cmd */
+#define SDCC3_CFG_RCGR              (CLK_CTL_BASE + 0x554) /* cfg */
+#define SDCC3_M                     (CLK_CTL_BASE + 0x558) /* m */
+#define SDCC3_N                     (CLK_CTL_BASE + 0x55C) /* n */
+#define SDCC3_D                     (CLK_CTL_BASE + 0x560) /* d */
+
 #endif

platform/mdm9x25/mdm9x25-clock.c

@@ -111,8 +111,8 @@ static struct pll_vote_clk gpll0_clk_src =
 /* UART Clocks */
 
 static struct vote_clk gcc_blsp1_ahb_clk = {
-	.cbcr_reg = BLSP1_AHB_CBCR,
-	.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
+	.cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
 	.en_mask = BIT(17),
 
 	.c = {
@@ -121,6 +121,98 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 	},
 };
 
+static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
+{
+	F(   144000,    cxo,  16,   3,  25),
+	F(   400000,    cxo,  12,   1,   4),
+	F( 20000000,  gpll0,  15,   1,   2),
+	F( 25000000,  gpll0,  12,   1,   2),
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F(200000000,  gpll0,   3,   0,   0),
+	F_END
+};
+
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC2_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC2_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC2_M,
+	.n_reg        = (uint32_t *) SDCC2_N,
+	.d_reg        = (uint32_t *) SDCC2_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_4_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc2_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC2_APPS_CBCR,
+	.parent       = &sdcc2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC2_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc2_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk sdcc3_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC3_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC3_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC3_M,
+	.n_reg        = (uint32_t *) SDCC3_N,
+	.d_reg        = (uint32_t *) SDCC3_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_4_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc3_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_sdcc3_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC3_APPS_CBCR,
+	.parent       = &sdcc3_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc3_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc3_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC3_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc3_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
 {
 	F( 3686400,  gpll0,    1,  96,  15625),
@@ -282,6 +374,11 @@ static struct clk_lookup mdm_9625_clocks[] =
 	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
 	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
 
+	CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+	CLK_LOOKUP("sdc2_core_clk",  gcc_sdcc2_apps_clk.c),
+
+	CLK_LOOKUP("sdc3_iface_clk", gcc_sdcc3_ahb_clk.c),
+	CLK_LOOKUP("sdc3_core_clk",  gcc_sdcc3_apps_clk.c),
 };
 
 

platform/mdm9x25/platform.c

@@ -35,6 +35,7 @@
 #include <mmu.h>
 #include <arch/arm/mmu.h>
 #include <platform/iomap.h>
+#include <platform/clock.h>
 #include <target.h>
 #include <smem.h>
 #include <reg.h>

platform/msm_shared/qpic_nand.c

@@ -70,6 +70,7 @@ static uint32_t val;
 
 static struct flash_id supported_flash[] = {
 	/* Flash ID  Flash ID2 ID Mask     ID Mask2  Density(MB)    Wid Pgsz    Blksz              oobsz   8-bit ECCf */
+	{0x1590aa2c, 0,		   0xFFFFFFFF, 0x0,		 (256 << 20),   0,  2048,   (2048 << 6),       0x40,   0},
 	{0x1590AC2C, 0x56,     0xFFFFFFFF, 0xFF,     0x20000000,    0,  2048,   0x00020000,        0x40,   0},
 	{0x1590AC2C, 0x57,     0xFFFFFFFF, 0xFF,     0x20000000,    0,  2048,   0x00020000,        0x40,   1},
 	{0x1590AA2C, 0x06,     0xFFFFFFFF, 0x0,      0x10000000,    0,  2048,   0x00020000,        0xE0,   0},
@@ -1261,7 +1262,7 @@ qpic_nand_non_onfi_probe(struct flash_info *flash)
 	qpic_nand_fetch_id(flash);
 
 	/* Check if we support the device */
-	for (index = 0; index < (ARRAY_SIZE(supported_flash)); index++)
+	for (index = 1; index < (ARRAY_SIZE(supported_flash)); index++)
 	{
 		if (((flash->id & supported_flash[index].mask) ==
 		    (supported_flash[index].flash_id & (supported_flash[index].mask))) &&
@@ -1328,12 +1329,23 @@ void
 qpic_nand_init(struct qpic_nand_init_config *config)
 {
 	uint32_t i;
+	int nand_ret;
 
 	nand_base = config->nand_base;
 
 	qpic_bam_init(config);
 
-	qpic_nand_non_onfi_probe(&flash);
+	/* Do an ONFI probe. */
+	nand_ret = qpic_nand_onfi_probe(&flash);
+
+	if (nand_ret == NANDC_RESULT_DEV_NOT_SUPPORTED)
+	{
+		/* Not an ONFI Device.
+		 * Check if it is one of the devices we support.
+		 */
+		 qpic_nand_non_onfi_probe(&flash);
+
+	}
 
 	/* Save the RAW and read/write configs */
 	qpic_nand_save_config(&flash);

platform/msm_shared/rules.mk

@@ -368,7 +368,8 @@ ifeq ($(PLATFORM),mdm9x25)
 			$(LOCAL_DIR)/dev_tree.o \
 			$(LOCAL_DIR)/clock.o \
 			$(LOCAL_DIR)/clock_pll.o \
-			$(LOCAL_DIR)/clock_lib2.o
+			$(LOCAL_DIR)/clock_lib2.o \
+			$(LOCAL_DIR)/regulator.o
 endif
 
 ifeq ($(PLATFORM),mdm9x35)

project/lk2nd-mdm9625.mk

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: BSD-3-Clause
+TARGET := mdm9625
+include lk2nd/project/lk2nd.mk

target/mdm9625/init.c

@@ -29,6 +29,8 @@
 #include <debug.h>
 #include <board.h>
 #include <platform.h>
+#include <uart_dm.h>
+#include <spmi.h>
 #include <target.h>
 #include <smem.h>
 #include <baseband.h>