Worksop VHDL - FPGAs

Repo with our solutions for the assignments that come with the Workshop VHDL

Name		Name	Last commit message	Last commit date
Latest commit History 41 Commits
Week4_Thomas		Week4_Thomas
Week6_Thomas		Week6_Thomas
week1_Jelle		week1_Jelle
week1_Thomas		week1_Thomas
week2_Jelle		week2_Jelle
week2_Thomas		week2_Thomas
week3_Jelle		week3_Jelle
week3_Thomas		week3_Thomas
week5_Jelle		week5_Jelle
week5_Thomas		week5_Thomas
week6_Jelle		week6_Jelle
week7_Thomas		week7_Thomas
.gitignore		.gitignore
README.md		README.md

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