[top] Restructure chiplevel hierarchies#30387
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Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
This commit moves the dummy padring for Verilator from the testbench to the chiplevel, and replaces the connections to/from the DPI modules with hierarchical module references (XMRs). Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
This commit adds the missing englishbreakfast chiplevel for Verilator, and adapts the tb to instantiate it. Like for earlgrey in the preceeding commits, this includes a Verilator-specific padring and a few additional branches in the shared chiplevel template. Since the combined tb and chiplevel did not include the real ast up until this point, the respective lint collateral for ast is linked to earlgrey. Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
This commit is analogous to the preceeding ones but applies the changes to darjeeling. Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
!!REMOVE this commit before PR!! Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
In accordance with the power domain reorganization RFC, this commit
consistently names the toplevel power domain HDL modules
`{topname}_pd_{domain}`. This mainly means that all the `top_{topname}`
modules are now called `{topname}_pd_main`, i.e., the default power
domain no longer has a special name for the corresponding HDL module.
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
After the recent power domain reorganization (lowRISC#30076), the HDL paths in the generated RAL collateral require knowledge about the power domain of each IP. This issue so far hasn't shown itself since so far the path to the main power domain wasn't changed, and the chip level dv env did not do any RAL-based accesses to IPs in the Aon domain. Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
With `top_{topname}` being renamed to `{topname}_pd_{domain}` in the
preceeding commit, this one reintroduces `top_{topname}` as an
additional level of hierarchy that wraps all "core" logic:
- All power domains (or more precisely, their wrappers)
- AST - split/absorption into the above still pending
- Any FPGA glue logic
The chiplevels now only instantiate the module described above and any
hard macros, such as pad cells or e.g., the USB differential receiver.
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
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