Enable pd-disaggregation benchmark on Intel XPU - #1513
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Add an Intel XPU (gpu.intel.com/xe, classic device plugin) variant of the pd-disaggregation guide so the prefill/decode-disaggregated scenario runs on Intel GPUs. - config/scenarios/guides/pd-disaggregation-xpu.yaml: XPU scenario with prefill+decode pools, NixlConnector KV transfer (kv_buffer_device=cpu, UCX_TLS=tcp for Intel GPUs without GPUDirect/cuda_ipc), --enforce-eager, float16, RWO storage for kind, podSecurityContext supplementalGroups for /dev/dri access, Qwen3-0.6B, TP1, prefill replicas:1 + decode replicas:1. - config/specification/guides/pd-disaggregation-xpu.yaml.j2: spec pointing at the XPU scenario (mirrors pd-disaggregation.yaml.j2). Note: depends on the decode/prefill podSecurityContext indent fix in config/templates/jinja/13_ms-values.yaml.j2 from the optimized-baseline-xpu change set. Signed-off-by: WenjiaoYue <wenjiao.yue@intel.com>
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achandrasekar,
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mengmeiye and
namasl
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June 17, 2026 15:50
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Pull request overview
Enables running the existing P/D disaggregation guide benchmark configuration on Intel XPU (classic gpu.intel.com/xe device plugin) by adding an XPU-specific scenario plus a matching specification entry that points the renderer at that scenario.
Changes:
- Add a new
pd-disaggregation-xpuscenario tuned for Intel XPU (image override, Intel GPU resource, TCP UCX transport, CPU KV buffer device, eager execution, kind-friendly RWO PVCs). - Add a new spec template that mirrors the existing
pd-disaggregationspec but selects the new XPU scenario file.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 3 comments.
| File | Description |
|---|---|
| config/specification/guides/pd-disaggregation-xpu.yaml.j2 | New renderer spec pointing to the XPU scenario. |
| config/scenarios/guides/pd-disaggregation-xpu.yaml | New Intel XPU P/D disaggregation scenario (resources, vLLM commands, routing, storage, security context). |
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| podSecurityContext: | ||
| supplementalGroups: | ||
| - 107 |
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| # Pod-level securityContext. Group 107 = render, for /dev/dri. See the | ||
| # prefill note above for why runAsUser/runAsGroup are NOT set here. | ||
| podSecurityContext: | ||
| supplementalGroups: | ||
| - 107 |
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| # ROUTING - NIXL v2 connector drives prefill->decode KV-cache transfer. | ||
| # The preprocess init container auto-populates the NIXL side-channel env | ||
| # (VLLM_NIXL_*) at pod runtime; we only pin UCX transport to TCP below | ||
| # (vllmCommon.ucxTls), which is the XPU-supported NIXL transport. |
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This PR is marked as stale after 21d of inactivity. After an additional 14d of inactivity (7d to become rotten, then 7d more), it will be closed. To prevent this PR from being closed, add a comment or remove the |
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Enable pd-disaggregation benchmark on Intel XPU.
Note: depends on the decode/prefill podSecurityContext indent fix in config/templates/jinja/13_ms-values.yaml.j2 from the optimized-baseline-xpu change set.