PoliLEG is a VHDL implementation of the LEGv8 processor subset introduced by Hennessy and Patterson. It uses a single-cycle Harvard architecture, with separate instruction and data memories, and completes every instruction in one clock cycle.
The project implements the complete datapath and control path, including the program counter, register file, ALU, immediate-generation and branch logic, and memory interfaces.
PoliLEG follows the classic separation between a datapath and a control unit. The datapath stores and transforms values through components such as the program counter, register file, ALU, memories, sign-extension unit, and multiplexers. The control unit decodes each instruction and generates the signals that select the required operation and route data through those components.
Together, these two parts perform the instruction cycle: fetch, decode, execute, memory access, and write-back. Because PoliLEG is a single-cycle processor, the entire cycle is completed within one clock period. This keeps the control logic straightforward, although the clock period must be long enough for the slowest supported instruction to finish.
PoliLEG supports the following instructions:
Language note: The table retains the Portuguese headers Instrução, Formato, and Sintaxe/Descrição because it is an original project artifact. They mean Instruction, Format, and Syntax/Description, respectively.
- D-format for LDUR and STUR
- R-format for ADD, SUB, AND, and ORR
- CB-format for CBZ
- B-format for B
PoliLEG consists of several functional units:
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Memory
- Instruction memory (IM) stores instructions.
- Data memory (DM) stores data.
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Register
- The PC (program counter).
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Register file
- Stores the registers used by instructions.
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ALU (arithmetic logic unit)
- Performs arithmetic and logical operations.
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Multiplexers
- Route data to the appropriate units.
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Sign extension
- Extends signed values when required.
The program stored in ROM (rom.dat) computes the greatest common divisor (GCD). The GCD algorithm's parameters are stored in RAM (ram.dat):
- Address 0: a constant representing the most negative two's-complement value.
- Address 1: the first GCD parameter (A).
- Address 2: the second GCD parameter (B).
The program reads A and B, computes their GCD, and stores the result at address 0, replacing the constant.
Compatibility note: The final RAM and ROM contents do not exactly follow the project specification, because they were adapted to the implemented processor's word size, addressing, and related constraints.
Language note: The linked specification is in Brazilian Portuguese because it is the original assignment issued for the PCS3225 Digital Systems II course at the University of São Paulo; no official English version was provided with this project.
Language note: The processor documentation and project specification are in Brazilian Portuguese because they are preserved original course materials. The Green Card and assembly source are in English.