arch: add TriCore architecture and Infineon AURIX platform support

Documentation/platforms/tricore/index.rst

@@ -2,40 +2,49 @@
 TriCore
 =======
 
-All TriCore source reside in lower-level common, chip-specific, and architecture-specific
-directories.
-
-arch/tricore/src/common/ Directory
-==================================
-
-This directory holds source files common to all TriCore architectures.
-
-Architecture-Specific Directories
-=================================
-
-Architecture-specific directories hold common source files shared for by
-implementations of specific TriCore architectures.
-
-``TriCore``
-  This directory holds logic appropriate for any instantiation of the 32-bit
-  TriCore architecture.
-
-Chip-Specific directories
-=========================
-
-For SoC chips, in particular, on-chip devices and differing interrupt
-structures may require special, chip-specific definitions in these chip-
-specific directories.
-
-The core Chip implementation is based on Infineon Low Level Drivers (iLLDs).
-The unified API is more friendly to developers familiar with Infineon SDK/HAL.
-We can get more code examples on Infineon's official Github: `AURIX_code_examples <https://github.com/Infineon/AURIX_code_examples>`__
-
-``TC3xx/TC4xx``
-  This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx/TC4xx microcontroller family.
+NuttX runs on Infineon AURIX TriCore microcontrollers in flat 32-bit address
+mode.  The port is implemented entirely with direct SFR access; there is no
+dependency on Infineon's iLLD SDK, low-level startup is provided by NuttX.
+
+The port covers two AURIX SoC families:
+
+================ ================ =====================
+ Family           TriCore ISA      ARCH_FAMILY
+================ ================ =====================
+ TC3X (TC1.6.2)   TC162            ``tc1v6``
+ TC4X (TC1.8)     TC18             ``tc1v8``
+================ ================ =====================
+
+Common features:
+
+- Runs in Supervisor Mode on CPU0.
+- IRQs routed by the Interrupt Router (IR), per-Service-Request-Node SRC
+  registers; SRPN equals the IRQ number.
+- System Timer (STM) drives the NuttX systick (oneshot lower-half).
+- ASCLIN-based UART for the NSH console.
+- GPIO pinmuxing for both families through a shared aurix layer.
+- HighTec LLVM 10.2.0 (clang -target tricore) and tricore-elf-gcc 11.3.1
+  toolchains are both supported.
+
+Source layout
+=============
+
+::
+
+  arch/tricore/
+    include/{tc3x,tc4x}/    chip-public headers
+    src/
+      common/               core arch (boot, traps, IRQs, scheduling)
+      aurix/                shared peripherals (ASCLIN UART, GPIO)
+      tc3x/                 TC3X-specific (clock tree, ENDINIT, GPIO)
+      tc4x/                 TC4X-specific (clock tree, GPIO)
+
+Supported boards
+================
 
 .. toctree::
    :maxdepth: 1
    :glob:
 
-   */*
+   tc3x/*
+   tc4x/*

Documentation/platforms/tricore/tc3x/index.rst

@@ -0,0 +1,16 @@
+==========
+AURIX TC3X
+==========
+
+NuttX support for the Infineon AURIX TC3X (TriCore TC1.6.2) family.
+
+The TC3X port covers SCU clock tree bring-up (PLL, CCU dividers, ENDINIT
+password rotation), the IR/SRC interrupt routing, the System Timer (STM)
+oneshot and ASCLIN-based UART.  Boards select a particular TC3X variant
+through ``CONFIG_TC3X_CHIP_*``.
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   */*

Documentation/platforms/tricore/tc4x/index.rst

@@ -0,0 +1,17 @@
+==========
+AURIX TC4X
+==========
+
+NuttX support for the Infineon AURIX TC4X (TriCore TC1.8) family.
+
+The TC4X port covers SCU clock tree bring-up (PLL, CCU dividers,
+SafetyEndInit/CpuEndInit unlock), the IR/SRC interrupt routing
+(SRPN equals the IRQ number), the System Timer (STM) oneshot and
+ASCLIN-based UART.  Boards select a particular TC4X variant through
+``CONFIG_TC4X_CHIP_*``.
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   */*