[59F5SP] Release v1.0.0

RV64I59F_5SP_SoC release v1.0.0

The very first release of ima_make_rv64 core design.

^{59F5SP_SoC's signal-level block diagram.}

What's included?

• RV64I59F_5SP and its submodules' main core RTL code written in verilog.
• Testbench source codes for each modules in core design.
• Testbench results with vvp and vcd files.
  RV64I59F_5SP's top module testbench scenario is integrated in Instruction memory.
• 59F5SP_SoC top module which integrates RV64I59F_5SP core with MMIO UART control modules.

What is this?

FPGA synthesizable RTL source codes of RV64I 5-Stage Pipelined processor RV64I59F_5SP and its SoC configuration modules.
You can simply run behavior simulation with iverilog and see waveforms via GTKwave or Sufer project.
In FPGA, you can benchmark the core module with Dhrystone 2.1 and Coremark with button and get result by LEDs and MMIO UART TX communication. (115200baud)

• Up button for Benchmark Start.
• LED[0] on : benchmark ready (not executing)
• LED[1]~LED[7] : opcode of instruction[6:0]

For FPGA project in Vivado, get Package release for setup the environment with .xpr project file.

Performance @ 50MHz

• Dhrystone 2.1 : 1.15 DMIPS/MHz

• Coremark : 0.92 Coremarks/MHz

What's Changed

• Implement ALU with multiplication by @ChoiCube84 in #1
• Implement Program Counter module by @ChoiCube84 in #2
• Implement Instruction Decoder module by @ChoiCube84 in #3
• Implement PCPlus4 module by @ChoiCube84 in #4
• Implement Register File module by @ChoiCube84 in #5
• Implement ALU Controller module by @ChoiCube84 in #6
• Implement Byte Enable Logic module by @ChoiCube84 in #7
• Implement Immediate Generator module by @ChoiCube84 in #8
• [Feat] Upload existing headers from basic_RV32s by @T410N in #9
• [Feat] Revise Program Counter by Parameterizing with XLEN and its testbench by @T410N in #10
• [Feat] Revise Instruction Decoder 6-bit shamt logic and its testbench by @T410N in #11
• [Feat] Revise Instruction Decoder testbench vcd output by @T410N in #12
• [Feat] Implement Instruction Memory with RV64 bit width revision and its testbench by @T410N in #13
• [Feat] Implement IF ID Register file with 64-bit XLEN and its testbench by @T410N in #14
• [Feat] Implement PC Controller with 64-bit XLEN and its testbench by @T410N in #15
• [Feat] Implement Branch Predictor with 64-bit XLEN width and its testbench by @T410N in #16
• [Feat] Revise Register File by parameterizing with 64-bit XLEN and its testbench by @T410N in #19
• [Feat] Revise Immediate Generator by Parameterizing with 64-bit XLEN by @T410N in #20
• [Feat] Implement Exception Detector and its testbench by @T410N in #17
• [Feat] Implement Control Unit and its testbench by @T410N in #21
• [Feat] Implement Hazard Unit and its testbench by @T410N in #25
• [Feat] Implement Trap Controller and its 64-bit XLEN testbench by @T410N in #18
• [Feat] Implement ID EX Register with 64-bit XLEN and its testbench by @T410N in #23
• [Feat] Implement Branch Logic with 64-bit XLEN parameter and its testbench by @T410N in #24
• [Feat] Implement CSR File and its testbench by @T410N in #22
• [Feat] Revise ALU functions and added XLEN parameter with its testbench by @T410N in #27
• [Feat] Implement Forward Unit and its testbench by @T410N in #29
• [Feat] Revise Byte Enable Logic by adding 64-bit XLEN parameter by @T410N in #32
• [Feat] Revise ID EX Register by increasing rs2 bit width to 6-bit by @T410N in #34
• [Feat] Revise CSR File by fixing typos by @T410N in #35
• [Feat] Revise Hazard Unit for proper data hazard detection by @T410N in #36
• [Feat] Implement EX MEM Register and its testbench by @T410N in #28
• [Feat] Implement Data Memory and its testbench by @T410N in #30
• [Feat] Implement MEM WB Register and its testbench by @T410N in #31
• [Feat] Implement draft RV64I59F_5SP top module and its draft testbench by @T410N in #33
• [Feat] Revise Data Memory's ram_address alignment 14:2 to 15:3 due to 64-bit XLEN by @T410N in #39
• [Feat] Revise EX MEM Register by adding rs2 signal pipeline by @T410N in #40
• [Feat] Revise ALU Controller by refactoring codes and reducing latch infers by @T410N in #37
• [Feat] Revise Forward Unit by adding retired to EX forwarding logic by @T410N in #41
• [Feat] Revise Hazard Unit making it capable of wb to mem hazard and retire hazard by @T410N in #42
• [Feat] Revise Instruction Decoder by revising shifting instructions decoding logic by @T410N in #43
• [Feat] Revise Byte Enable Logic Partial byte level Load logics and refactored codes by @T410N in #38
• [Feat] Revise RV64I59F_5SP Top module by applying submodules changes by @T410N in #44
• [Feat] Remove mislocated testbench vcd output file of mem_wb_register by @T410N in #45
• [Feat] Add RV64I59F_5SP FPGA Vivado project file by @T410N in #46
• [Feat] Add SoC sub modules for RV64I59F_5SP - 59F5SP_SoC by @T410N in #47
• [Feat] Revise FPGA ID EX Register rs2 bit width when reset by @T410N in #48
• [Feat] Revise EX MEM Register rs2 pipeline bit width from 6-bit to 5-bit by @T410N in #49
• [Feat] Revise ALU DWORD and WORD shift bit slicing properly by @T410N in #50
• [Feat] Revise RV64I59F_5SP top module MEM_rs2 bit width to 5-bit by @T410N in #51
• [Feat] Revise Instruction Memory annotations to RV64I version by @T410N in #52
• [Feat] Implement RV64I59F_5SP top module and its testbench by @T410N in #53
• Revert "[Feat] Revise Instruction Memory annotations to RV64I version" by @T410N in #54
• [Feat] Revise Instruction Memory annotations to RV64I version by @T410N in #55
• [Feat] Implement RV64I59F_5SP and its testbench by @T410N in #56
• [Feat] Revise SoC submodules by adding line break between end else by @T410N in #58
• [Feat] Revise IF ID Register by adding line break between end else by @T410N in #59
• [Feat] Revise Instruction Memory by adding line break between end else by @T410N in #60
• [Docs] Update devlog and README by @T410N in #61
• [Feat] Revise FPGA sub modules by adding line break between end else by @T410N in #62
• [Feat] Implement RV64I59F_5SP Top module and 59F5SP_SoC FPGA by @T410N in #57

New Contributors

• @ChoiCube84 made their first contribution in #1
• @T410N made their first contribution in #9

Full Changelog: https://github.com/RISC-KC/ima_make_rv64/commits/v1.0.0