suport stash - #25
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- mill -> 0.12.17 - chisel -> 7.13.0 - update github workflow
zzQGyy
requested review from
Ivyfeather,
Kumonda221-CrO3,
Maxpicca-Li and
linjuanZ
as code owners
July 23, 2026 03:22
Move L3 stash prefetch request handling out of Prefetcher.scala into StashPrefetcher.scala. Keep the Prefetcher top-level wiring focused on connecting the L3 receive path and SLC CHI channels. Limit the stash prefetch inflight entries to 16 instead of reusing the global L2 prefetch inflight maximum. This keeps the stash queue depth independent from PrefetchReceiverParams. Lower the stash prefetch CHI QoS to 0 so speculative L3 stash traffic does not compete with demand and MMIO TXREQs at the highest QoS level. Rename the stash entry FSM states to camelCase to match local Scala naming style. Validation: - mill -i XSCache.compile
Rework openLLC L3 prefetch perf counters to count accepted `busTask_s1.fire` events for hit and late observations. Remove the narrow `*Cycles` counters and replace the previous-cycle de-dup logic with a shared same-address helper. Keep `stashOnceSharedOriginalRNHit` visible in `MainPipe` as a redundant L3 stash prefetch observation point.
Rename the stash CHI ports to `stash_txreq` and `stash_rxrsp` at the prefetch boundary, and keep the CoupledL2 transaction-ID layout explicit with named `mmioFlag`, `sliceId`, `stashFlag`, and `entryID` fields.
StashOnceShared refill can allocate both ResponseUnit and RefillUnit entries while MainPipe sends a ReadNoSnp to MemUnit. If that read hits a same-line pending WriteNoSnpFull, MemUnit forwards the line through bypassData instead of issuing a downstream read. The bypass data was only consumed by ResponseUnit, so the RefillUnit entry could keep waiting for downstream RXDAT and eventually trigger a RefillBuf Leak assertion. Connect MemUnit bypassData to RefillUnit and update matching StashOnceShared refill entries from the bypass beats. RefillUnit now checks for a single bypass TxnID and rejects mixed data sources. Add a StashPrefetchEntry leak timer to catch long waits for CHI responses. Also tighten stash prefetch TxnID namespace checks so normal request IDs cannot overlap the stash flag.
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