OpenXiangShan
diff --git a/‎configs/common/Options.py‎
Lines changed: 47 additions & 0 deletions b/‎configs/common/Options.py‎
Lines changed: 47 additions & 0 deletions
diff --git a/‎configs/common/xiangshan.py‎
Lines changed: 221 additions & 11 deletions b/‎configs/common/xiangshan.py‎
Lines changed: 221 additions & 11 deletions
@@ -37,6 +37,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import argparse
+import sys
 
 import m5
 from m5.defines import buildEnv
@@ -672,3 +673,49 @@ def addXiangshanFSOptions(parser):
                         action="store",
                         default=None,
                         help="The shared lib file used to do difftest")
+
+def addXiangshanTraceOptions(parser):
+    # Add trace-specific arguments for trace-driven simulation
+    parser.add_argument('--enable-trace-mode', action='store_true',
+                       help='Enable trace-driven simulation mode (alternative to checkpoints)')
+    parser.add_argument('--trace-timing-ptw', action='store_true',
+                       help='In trace mode, use timing TLB/PTW (static page table; default: off)')
+    parser.add_argument('--trace-ptw-reserved-bytes', type=int,
+                       default=64 * 1024 * 1024,
+                       help='Bytes reserved at top of trace-mapped memory for page tables (default: 64MiB)')
+    parser.add_argument('--trace-ptw-page-size', type=str, default='4k',
+                       choices=['4k', '2m'],
+                       help='Synthetic mapping page size for trace timing PTW (default: 4k)')
+    parser.add_argument('--trace-file', type=str,
+                       help='Path to the trace file (required for trace mode)')
+    parser.add_argument('--trace-format', type=str, default='champsim',
+                       choices=['champsim', 'cbp2025'],
+                       help='Trace format (default: champsim)')
+    # Use the common --maxinsts option provided by common Options; no trace-specific max
+
+    # Decoupled branch predictor options for trace mode
+    parser.add_argument('--trace-enable-decoupled-bp', action='store_true',
+                       help='Enable decoupled branch predictor in trace mode')
+    parser.add_argument('--trace-checkpoint-interval', type=int, default=64,
+                       help='Checkpoint interval for trace rollback (default: 64)')
+    parser.add_argument('--trace-disable-bp-validation', action='store_true',
+                       help='Disable branch predictor validation against trace')
+    parser.add_argument('--trace-mispredict-penalty', type=int, default=8,
+                       help='Cycles to penalize on mispredict (default: 8)')
+    parser.add_argument('--trace-disable-wrongpath', action='store_true',
+                       help='Disable explicit wrong-path injection (use stall model)')
+    parser.add_argument('--trace-wrongpath-use-traceinst', action='store_true',
+                       help='Wrong-path injection uses trace instructions with checkpoint/restore (default: NOPs)')
+
+    # NOTE: This heuristic relies on using real sys.argv with argparse. If a
+    # custom args list is passed to parse_args, the caller should adjust
+    # generic-rv-cpt's required flag explicitly instead of relying on this.
+    # Check for trace mode before parsing to make generic-rv-cpt conditional.
+    if '--enable-trace-mode' in sys.argv:
+        # In trace mode, make generic-rv-cpt optional by providing a dummy value.
+        # Find the generic-rv-cpt action and remove its required flag.
+        for action in parser._actions:
+            if action.dest == 'generic_rv_cpt':
+                action.required = False
+                action.default = "trace_mode_dummy"
+                break
@@ -1,4 +1,5 @@
 import argparse
+import os
 import sys
 
 import m5
@@ -58,16 +59,50 @@ class XiangshanECore2Read(XiangshanCore):
     numPhysRMiscRegs = 40
     scheduler = ECore2ReadScheduler()
 
-import argparse
-import os
+addToPath('../')
 
-import m5
-from m5.defines import buildEnv
-from m5.objects import *
-from m5.util import addToPath, fatal, warn
-from m5.util.fdthelper import *
+def _trace_timing_ptw_settings(args: argparse.Namespace):
+    enabled = bool(getattr(args, 'trace_timing_ptw', False))
+    if not enabled:
+        return False, 0, 0
 
-addToPath('../')
+    reserved_bytes = int(getattr(args, 'trace_ptw_reserved_bytes', 64 * 1024 * 1024))
+    if reserved_bytes <= 0:
+        fatal(f"--trace-ptw-reserved-bytes must be > 0 (got {reserved_bytes})")
+
+    page_size = getattr(args, 'trace_ptw_page_size', '4k')
+    if page_size == '4k':
+        leaf_page_size = 4 * 1024
+    elif page_size == '2m':
+        leaf_page_size = 2 * 1024 * 1024
+    else:
+        fatal(f"Unsupported --trace-ptw-page-size: {page_size}")
+
+    return True, reserved_bytes, leaf_page_size
+
+
+def _apply_trace_timing_ptw_cpu_params(args: argparse.Namespace, cpus, *, shrink_window: bool = True):
+    enabled, reserved_bytes, leaf_page_size = _trace_timing_ptw_settings(args)
+    if not enabled:
+        return
+
+    for cpu in cpus:
+        cpu.traceTimingPTW = True
+        cpu.tracePTReservedBytes = reserved_bytes
+        cpu.tracePTLeafPageSize = leaf_page_size
+
+    if not shrink_window:
+        return
+
+    for cpu in cpus:
+        if int(cpu.traceAddrSize) <= reserved_bytes:
+            fatal(
+                "Trace timing PTW requires traceAddrSize > reserved bytes "
+                f"(traceAddrSize=0x{int(cpu.traceAddrSize):x}, "
+                f"reserved=0x{reserved_bytes:x})."
+            )
+
+        cpu.traceAddrSize = int(cpu.traceAddrSize) - reserved_bytes
 
 
 def config_xiangshan_inputs(args: argparse.Namespace, sys):
@@ -209,13 +244,55 @@ def build_xiangshan_system(args):
     ruby = False
     if hasattr(args, 'ruby') and args.ruby:
         ruby = True
+
+    # Create system using FS mode with trace-specific memory configuration
     test_sys = makeBareMetalXiangshanSystem('timing', SysConfig(mem=args.mem_size), None, np=np, ruby=ruby)
+
+    # CRITICAL FIX: Configure trace-specific memory ranges and functional TLB for trace mode
+    if hasattr(args, 'enable_trace_mode') and args.enable_trace_mode:
+        if bool(getattr(args, 'trace_timing_ptw', False)):
+            print("Trace mode: Using FS mode with timing MMU (timing-PTW enabled)")
+        else:
+            print("Trace mode: Using FS mode with functional TLB to bypass MMU translation issues")
+        print("Trace mode: Configuring expanded memory ranges for trace address mapping")
+        # Force functional TLB to bypass complex MMU translation
+        args.functional_tlb = True
+    else:
+        print("Checkpoint mode: Using standard FS mode with normal MMU translation")
     test_sys.num_cpus = np
 
     test_sys.xiangshan_system = True
+    # args.enable_difftest should be normalized by xiangshan_system_init().
     test_sys.enable_difftest = args.enable_difftest
 
-    config_xiangshan_inputs(args, test_sys)
+    # Configure XiangShan inputs - skip checkpoint loading in trace mode
+    if hasattr(args, 'enable_trace_mode') and args.enable_trace_mode:
+        args.difftest_ref_so = None
+
+        # Trace mode FS configuration with functional TLB.
+        # We run without a bootloader but must still set the bootloader
+        # parameter explicitly, since RiscvBareMetal.bootloader has no
+        # default. An empty string is treated as "no bootloader" and we
+        # reuse the xiangshan_cpt flag to take the no-bootloader path in
+        # the BareMetal workload implementation.
+        test_sys.workload.bootloader = ''
+        test_sys.workload.xiangshan_cpt = True   # Reuse GCPT path to skip bootloader
+        test_sys.restore_from_gcpt = False       # Disable GCPT restoration
+        print("Trace mode: Running without bootloader (no GCPT)")
+
+        # Configure DRAMsim3 if needed for memory controller
+        if args.mem_type == 'DRAMsim3' and args.dramsim3_ini is None:
+            root_dir = os.path.dirname(os.path.dirname(os.path.dirname(__file__)))
+            args.dramsim3_ini = os.path.join(root_dir,
+                                             'ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_2ch.ini')
+
+        if bool(getattr(args, 'trace_timing_ptw', False)):
+            print("Trace mode: Timing MMU will be applied for timing-PTW")
+        else:
+            print("Trace mode: FS mode with functional TLB configured to bypass MMU translation issues")
+    else:
+        # Standard checkpoint-based configuration
+        config_xiangshan_inputs(args, test_sys)
 
      # Set the cache line size for the entire system
     test_sys.cache_line_size = args.cacheline_size
@@ -238,12 +315,19 @@ def build_xiangshan_system(args):
     # For now, assign all the CPUs to the same clock domain
     test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
                     for i in range(np)]
+    # Configure MMU for trace-aware FS mode
     for cpu in test_sys.cpu:
         cpu.mmu.pma_checker = PMAChecker(
             uncacheable=[AddrRange(0, size=0x80000000)])
         cpu.mmu.functional = args.functional_tlb
         cpu.mmu.enable_sv48 = args.open_sv48
 
+        if hasattr(args, 'enable_trace_mode') and args.enable_trace_mode:
+            timing_ptw = bool(getattr(args, 'trace_timing_ptw', False))
+            cpu.mmu.functional = not timing_ptw
+            mode_str = "timing" if timing_ptw else "functional"
+            print(f"Trace mode: CPU {cpu.cpu_id} configured with {mode_str} translation")
+
     # configure BP
     args.enable_loop_predictor = True
     if args.enable_riscv_vector:
@@ -296,6 +380,62 @@ def build_xiangshan_system(args):
 
     for cpu in test_sys.cpu:
         cpu.store_prefetch_train = not args.kmh_align
+
+    # Configure trace mode if enabled
+    if hasattr(args, 'enable_trace_mode') and args.enable_trace_mode:
+        if not getattr(args, 'trace_file', None):
+            fatal("--trace-file is required when --enable-trace-mode is set")
+        print(f"Configuring CPUs for trace mode...")
+        for cpu in test_sys.cpu:
+            # Enable trace mode
+            cpu.enableTraceMode = True
+            cpu.traceFile = args.trace_file
+            cpu.traceFormat = args.trace_format
+            # Unify with normal mode option: use --maxinsts
+            cpu.max_insts_any_thread = args.maxinsts
+
+            # Trace address mapping: Map to existing physical memory range
+            # System physical memory starts at 0x80000000, so map trace addresses there
+            cpu.traceAddrBase = 0x80000000  # Start of physical memory
+            cpu.traceAddrSize = 0x40000000  # 1GB window within physical memory
+
+            # Disable strict memory ordering for trace mode compatibility
+            # Trace instructions may not follow strict ordering requirements
+            cpu.needsTSO = False
+
+            # Trace mispredict modeling controls
+            cpu.traceMispredictPenalty = args.trace_mispredict_penalty
+            cpu.traceEnableWrongPath = (not args.trace_disable_wrongpath)
+            if hasattr(args, 'trace_wrongpath_use_traceinst') and args.trace_wrongpath_use_traceinst:
+                cpu.traceWrongPathUseTraceInst = True
+
+            # Note: Difftest configured at system level, not CPU level
+
+            # Configure trace-specific parameters
+            if hasattr(args, 'trace_enable_decoupled_bp') and args.trace_enable_decoupled_bp:
+                cpu.enableDecoupledBPInTrace = True
+            else:
+                cpu.enableDecoupledBPInTrace = False
+
+            cpu.traceCheckpointInterval = (args.trace_checkpoint_interval
+                                           if hasattr(args, 'trace_checkpoint_interval')
+                                           else 64)
+            cpu.traceBPValidation = not (hasattr(args, 'trace_disable_bp_validation')
+                                         and args.trace_disable_bp_validation)
+
+        _apply_trace_timing_ptw_cpu_params(args, test_sys.cpu, shrink_window=False)
+
+        print(f"  Trace file: {args.trace_file}")
+        print(f"  Trace format: {args.trace_format}")
+        print(f"  Max instructions: {args.maxinsts}")
+        print(f"  Decoupled BP: {hasattr(args, 'trace_enable_decoupled_bp') and args.trace_enable_decoupled_bp}")
+        if bool(getattr(args, 'trace_timing_ptw', False)):
+            print(
+                "  Timing PTW: enabled "
+                f"(ptw_page_size={getattr(args, 'trace_ptw_page_size', '4k')}, "
+                f"reserved_bytes=0x{int(getattr(args, 'trace_ptw_reserved_bytes', 0)):x})"
+            )
+
     # ruby will overwrite the store_prefetch_train
     if ruby:
         test_sys._dma_ports = []
@@ -323,6 +463,38 @@ def build_xiangshan_system(args):
             # Ruby D-cache does not support store prefetch yet
             cpu.store_prefetch_train = False
 
+        # Align trace address mapping window to physical memory size (Ruby path)
+        if hasattr(args, 'enable_trace_mode') and args.enable_trace_mode:
+            aligned_base = None
+            aligned_total = None
+            try:
+                base = int(test_sys.mem_ranges[0].start)
+                total = 0
+                for r in test_sys.mem_ranges:
+                    total += int(r.size())
+                for cpu in test_sys.cpu:
+                    cpu.traceAddrBase = base
+                    cpu.traceAddrSize = total
+                    cpu.traceAddrMapMode = "linear"
+                aligned_base = base
+                aligned_total = total
+            except Exception as e:
+                print(f"Warning: failed to align trace mapping to mem (Ruby path): {e}")
+            _apply_trace_timing_ptw_cpu_params(args, test_sys.cpu)
+            if aligned_base is not None:
+                final_size = int(test_sys.cpu[0].traceAddrSize)
+                reserved_bytes = int(getattr(args, 'trace_ptw_reserved_bytes', 0))
+                if bool(getattr(args, 'trace_timing_ptw', False)):
+                    print(
+                        f"Trace mode: Align trace mapping to mem: base=0x{aligned_base:x}, "
+                        f"size=0x{final_size:x} (reserved=0x{reserved_bytes:x})"
+                    )
+                else:
+                    print(
+                        f"Trace mode: Align trace mapping to mem: base=0x{aligned_base:x}, "
+                        f"size=0x{aligned_total:x}"
+                    )
+
     else:
         if args.caches or args.l2cache:
             # By default the IOCache runs at the system clock
@@ -354,6 +526,37 @@ def build_xiangshan_system(args):
 
         MemConfig.config_mem(args, test_sys)
 
+        # Align trace address mapping window to physical memory size (classic cache path)
+        if hasattr(args, 'enable_trace_mode') and args.enable_trace_mode:
+            aligned_base = None
+            aligned_total = None
+            try:
+                base = int(test_sys.mem_ranges[0].start)
+                total = 0
+                for r in test_sys.mem_ranges:
+                    total += int(r.size())
+                for cpu in test_sys.cpu:
+                    cpu.traceAddrBase = base
+                    cpu.traceAddrSize = total
+                aligned_base = base
+                aligned_total = total
+            except Exception as e:
+                print(f"Warning: failed to align trace mapping to mem: {e}")
+            _apply_trace_timing_ptw_cpu_params(args, test_sys.cpu)
+            if aligned_base is not None:
+                final_size = int(test_sys.cpu[0].traceAddrSize)
+                reserved_bytes = int(getattr(args, 'trace_ptw_reserved_bytes', 0))
+                if bool(getattr(args, 'trace_timing_ptw', False)):
+                    print(
+                        f"Trace mode: Align trace mapping to mem: base=0x{aligned_base:x}, "
+                        f"size=0x{final_size:x} (reserved=0x{reserved_bytes:x})"
+                    )
+                else:
+                    print(
+                        f"Trace mode: Align trace mapping to mem: base=0x{aligned_base:x}, "
+                        f"size=0x{aligned_total:x}"
+                    )
+
     if args.mmc_img:
         for mmc, cpu in zip(test_sys.mmcs, test_sys.cpu):
             mmc.cpt_bin_path = args.mmc_cptbin
@@ -495,6 +698,8 @@ def xiangshan_system_init():
     parser = argparse.ArgumentParser()
     Options.addCommonOptions(parser, configure_xiangshan=True)
     Options.addXiangshanFSOptions(parser)
+    Options.addXiangshanTraceOptions(parser)
+
     # Add the ruby specific and protocol specific args
     if '--ruby' in sys.argv:
         Ruby.define_options(parser)
@@ -504,7 +709,12 @@ def xiangshan_system_init():
     TestMemClass = Simulation.setMemClass(args)
 
     args.xiangshan_system = True
-    args.enable_difftest = True
+    # Only enable difftest if not in trace mode - trace mode doesn't need reference model verification
+    if not (hasattr(args, 'enable_trace_mode') and args.enable_trace_mode):
+        args.enable_difftest = True
+    else:
+        args.enable_difftest = False
+        print("Trace mode: Difftest disabled for trace execution")
     args.enable_riscv_vector = True
 
-    return args
+    return args