Skip to content

Commit 4f1d9ae

Browse files
committed
cpu-o3: Gem5 idealkmhv3 Specification rollback
Change-Id: I78aa7d7003ee5c2b20391170c50bfe5b5b6d4512
1 parent 3bbae89 commit 4f1d9ae

1 file changed

Lines changed: 10 additions & 8 deletions

File tree

configs/example/idealkmhv3.py

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ def setKmhV3IdealParams(args, system):
3434
cpu.fetchQueueSize = 64
3535

3636
# decode
37-
cpu.fetchToDecodeDelay = 5
37+
cpu.fetchToDecodeDelay = 6
3838
cpu.decodeWidth = 8
3939
cpu.enable_loadFusion = False
4040
cpu.enableConstantFolding = False
@@ -53,8 +53,8 @@ def setKmhV3IdealParams(args, system):
5353
cpu.scheduler = KMHV3Scheduler()
5454

5555
# rob
56-
cpu.commitWidth = 12
57-
cpu.squashWidth = 12
56+
cpu.commitWidth = 8
57+
cpu.squashWidth = 8
5858
cpu.phyregReleaseWidth = 8
5959
cpu.RobCompressPolicy = 'kmhv3'
6060
cpu.numROBEntries = 160
@@ -72,16 +72,16 @@ def setKmhV3IdealParams(args, system):
7272
cpu.valuePred = IdealConstantLVP()
7373

7474
# lsq
75-
cpu.LQEntries = 128
75+
cpu.LQEntries = 120
7676
cpu.SQEntries = 64
7777
cpu.RARQEntries = 96
7878
cpu.RAWQEntries = 56
7979
cpu.LoadCompletionWidth = 8
8080
cpu.StoreCompletionWidth = 4
8181
cpu.RARDequeuePerCycle = 4
8282
cpu.RAWDequeuePerCycle = 4
83-
cpu.SbufferEntries = 24
84-
cpu.SbufferEvictThreshold = 16
83+
cpu.SbufferEntries = 16
84+
cpu.SbufferEvictThreshold = 9
8585
cpu.store_prefetch_train = False
8686

8787
# branch predictor
@@ -112,8 +112,9 @@ def setKmhV3IdealParams(args, system):
112112
l2_wrapper.data_sram_banks = 2
113113
l2_wrapper.dir_sram_banks = 2
114114
l2_wrapper.pipe_dir_write_stage = 4
115-
l2_wrapper.dir_read_bypass = True
115+
l2_wrapper.dir_read_bypass = False
116116
for j in range(args.l2_slices):
117+
l2_wrapper.slices[j].inner_cache.wpu = NULL
117118
# Configure XSDRRIP replacement policy (DRRIP mode)
118119
# Each slice: 2MB/4 = 512KB, 8-way, 64B line → 1024 sets
119120
l2_wrapper.slices[j].inner_cache.replacement_policy = XSDRRIPRP(mode=2, num_sets=1024)
@@ -131,7 +132,8 @@ def setKmhV3IdealParams(args, system):
131132

132133
# l3 cache
133134
if args.l3cache:
134-
system.l3.mshrs = 128
135+
system.l3.mshrs = 64
136+
system.l3.num_slices = 4
135137

136138
if __name__ == '__m5_main__':
137139
FutureClass = None

0 commit comments

Comments
 (0)