dyn_inst.hh

/*
 * Copyright (c) 2010, 2016, 2021 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __CPU_O3_DYN_INST_HH__
#define __CPU_O3_DYN_INST_HH__

#include <algorithm>
#include <array>
#include <cstdio>
#include <deque>
#include <list>
#include <optional>
#include <string>

#include "base/refcnt.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exec_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/dyn_inst_xsmeta.hh"
#include "cpu/o3/lsq_unit.hh"
#include "cpu/o3/replay_events.hh"
#include "cpu/op_class.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
#include "debug/CommitTrace.hh"
#include "debug/DecoupleBP.hh"
#include "debug/HtmCpu.hh"
#include "debug/LoadPipeline.hh"
#include "debug/RiscvMisc.hh"
#include "sim/cur_tick.hh"

namespace gem5
{

class Packet;

namespace o3
{

class IssueQue;

class DynInst : public ExecContext, public RefCounted
{
  private:
    DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
            InstSeqNum seq_num, CPU *cpu);

  public:
    // The list of instructions iterator type.
    typedef typename std::list<DynInstPtr>::iterator ListIt;

    struct Arrays
    {
        size_t numSrcs;
        size_t numDests;

        RegId *flatDestIdx;
        VirtRegId *destIdx;
        VirtRegId *prevDestIdx;
        VirtRegId *srcIdx;
        uint8_t *readySrcIdx;
    };

    static void *operator new(size_t count, Arrays &arrays);
    static void  operator delete(void* ptr);

    /** BaseDynInst constructor given a binary instruction. */
    DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
            const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu);

    DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
            const StaticInstPtr &macroop, const PCStateBase &pc,
            const PCStateBase &pred_pc, InstSeqNum seq_num, CPU *cpu);

    /** BaseDynInst constructor given a static inst pointer. */
    DynInst(const Arrays &arrays, const StaticInstPtr &_staticInst,
            const StaticInstPtr &_macroop);

    ~DynInst();

    /** Executes the instruction.*/
    Fault execute();

    /** Initiates the access.  Only valid for memory operations. */
    Fault initiateAcc();

    /** Completes the access.  Only valid for memory operations. */
    Fault completeAcc(PacketPtr pkt);

    // create store data uop
    void buildStoreAddrUop();

    // create store data uop
    // call before buildStoreAddrUop
    DynInstPtr createStoreDataUop();

    /** The sequence number of the instruction. */
    InstSeqNum seqNum = 0;

    /** The StaticInst used by this BaseDynInst. */
    const StaticInstPtr staticInst;

    /** the xs metadata for this instruction */
    const XsDynInstMetaPtr xsMeta;

    /** Pointer to the Impl's CPU object. */
    CPU *cpu = nullptr;

    BaseCPU *getCpuPtr() { return cpu; }

    /** Pointer to the thread state. */
    ThreadState *thread = nullptr;

    /** The kind of fault this instruction has generated. */
    Fault fault = NoFault;

    /** InstRecord that tracks this instructions. */
    Trace::InstRecord *traceData = nullptr;

    /** Whether this dynamic instruction is the last one in the trace stream. */
    bool lastTraceInstFlag = false;

  protected:
    enum Status
    {
        RobEntry,                /// Instruction is in the ROB
        LsqEntry,                /// Instruction is in the LSQ
        Completed,               /// Instruction has completed
        ResultReady,             /// Instruction has its result

        // scheduler state begin
        CanIssue,                /// Instruction can issue and execute
        MemDepSolved,            /// Memory dependencies are solved
        InReadyQue,              /// Instruction is in the ready queue
        Canceled,                /// Instruction is canceled
        Scheduled,               /// Instruction is scheduled
        ArbFailed,
        Issued,                  /// Instruction has issued
        // scheduler state end

        // load/store pipe state begin
        InPipe,
        CacheHit,
        WakeUpEarly,
        FullForward,
        LocalAccess,
        NeedReplay,
        SkipRawCheck,
        SkipFollowingPipe,

        // load/store pipe state end

        Executed,                /// Instruction has executed
        CanCommit,               /// Instruction can commit
        AtCommit,                /// Instruction has reached commit
        Committed,               /// Instruction has committed
        Squashed,                /// Instruction is squashed
        SquashedInIQ,            /// Instruction is squashed in the IQ
        SquashedInLSQ,           /// Instruction is squashed in the LSQ
        SquashedInROB,           /// Instruction is squashed in the ROB
        PinnedRegsRenamed,       /// Pinned registers are renamed
        PinnedRegsWritten,       /// Pinned registers are written back
        PinnedRegsSquashDone,    /// Regs pinning status updated after squash
        RecoverInst,             /// Is a recover instruction
        BlockingInst,            /// Is a blocking instruction
        ThreadsyncWait,          /// Is a thread synchronization instruction
        SerializeBefore,         /// Needs to serialize on
                                 /// instructions ahead of it
        SerializeAfter,          /// Needs to serialize instructions behind it
        SerializeHandled,        /// Serialization has been handled
        NumStatus
    };

    enum Flags
    {
        NotAnInst,
        TranslationStarted,
        TranslationCompleted,
        NormalLd,
        WaitingCacheRefill,
        HasPendingCacheReq,
        PossibleLoadViolation,
        HitExternalSnoop,
        EffAddrValid,
        RecordResult,
        LockedWriteSuccess,
        Predicate,
        MemAccPredicate,
        PredTaken,
        IsStrictlyOrdered,
        ReqMade,
        MemOpDone,
        HtmFromTransaction,
        IsEmptyMov,
        IsConstantFolded,
        MaxFlags
    };

  private:
    /* An amalgamation of a lot of boolean values into one */
    std::bitset<MaxFlags> instFlags;

    /** The status of this BaseDynInst.  Several bits can be set. */
    std::bitset<NumStatus> status;

    /* replay type of this instruction */
    std::optional<LdStReplayType> replayType;

  protected:
    /** The result of the instruction; assumes an instruction can have many
     *  destination registers.
     */
    std::queue<InstResult> instResult;

    /** PC state for this instruction. */
    std::unique_ptr<PCStateBase> pc;

    /** Values to be written to the destination misc. registers. */
    std::vector<RegVal> _destMiscRegVal;

    /** Indexes of the destination misc. registers. They are needed to defer
     * the write accesses to the misc. registers until the commit stage, when
     * the instruction is out of its speculative state.
     */
    std::vector<short> _destMiscRegIdx;

    size_t _numSrcs;
    size_t _numDests;

    // Flattened register index of the destination registers of this
    // instruction.
    RegId *_flatDestIdx;

    // Physical register index of the destination registers of this
    // instruction.
    VirtRegId *_destIdx;

    // Physical register index of the previous producers of the
    // architected destinations.
    VirtRegId *_prevDestIdx;

    // Physical register index of the source registers of this instruction.
    VirtRegId *_srcIdx;

    // Whether or not the source register is ready, one bit per register.
    uint8_t *_readySrcIdx;

    uint64_t amoOldGoldenValue;

  public:
    size_t numSrcs() const { return _numSrcs; }
    size_t numDests() const { return _numDests; }

    // Returns the flattened register index of the idx'th destination
    // register.
    const RegId &
    flattenedDestIdx(int idx) const
    {
        return _flatDestIdx[idx];
    }

    // Flattens a destination architectural register index into a logical
    // index.
    void
    flattenedDestIdx(int idx, const RegId &reg_id)
    {
        _flatDestIdx[idx] = reg_id;
    }

    // Returns the physical register index of the idx'th destination
    // register.
    PhysRegIdPtr
    renamedDestIdx(int idx) const
    {
        return _destIdx[idx].PhyReg();
    }

    VirtRegId
    extRenamedDestIdx(int idx) const
    {
        return _destIdx[idx];
    }

    // Set the renamed dest register id.
    void
    renamedDestIdx(int idx, VirtRegId phys_reg_id)
    {
        _destIdx[idx] = phys_reg_id;
    }

    // Returns the physical register index of the previous physical
    // register that remapped to the same logical register index.
    VirtRegId
    prevDestIdx(int idx) const
    {
        return _prevDestIdx[idx];
    }

    // Set the previous renamed dest register id.
    void
    prevDestIdx(int idx, VirtRegId phys_reg_id)
    {
        _prevDestIdx[idx] = phys_reg_id;
    }

    // Returns the physical register index of the i'th source register.
    PhysRegIdPtr
    renamedSrcIdx(int idx) const
    {
        return _srcIdx[idx].PhyReg();
    }

    VirtRegId
    extRenamedSrcIdx(int idx) const
    {
        return _srcIdx[idx];
    }

    void
    renamedSrcIdx(int idx, VirtRegId phys_reg_id)
    {
        _srcIdx[idx] = phys_reg_id;
    }

    // after dispatch, it's status was speculative
    bool
    readySrcIdx(int idx) const
    {
        uint8_t &byte = _readySrcIdx[idx / 8];
        return bits(byte, idx % 8);
    }

    void
    readySrcIdx(int idx, bool ready)
    {
        uint8_t &byte = _readySrcIdx[idx / 8];
        replaceBits(byte, idx % 8, ready ? 1 : 0);
    }

    /** The thread this instruction is from. */
    ThreadID threadNumber = 0;

    /** Iterator pointing to this BaseDynInst in the list of all insts. */
    ListIt instListIt;

    ////////////////////// Branch Data ///////////////
    /** Predicted PC state after this instruction. */
    std::unique_ptr<PCStateBase> predPC;

    Addr fallThruPC;

    /** ftqId is used for squashing and committing */
    /** The fetch stream queue ID of the instruction. */
    unsigned ftqId;
    /** The number of loop iteration within an fsq entry of the instruction. */
    unsigned loopIteration;

    /** The Macroop if one exists */
    const StaticInstPtr macroop;

    /** How many source registers are ready. */
    uint8_t readyRegs = 0;

  public:
    /////////////////////// Load Store Data //////////////////////
    /** The effective virtual address (lds & stores only). */
    Addr effAddr = 0;

    /** The effective physical address. */
    Addr physEffAddr = 0;

    /** The memory request flags (from translation). */
    unsigned memReqFlags = 0;

    /** The size of the request */
    unsigned effSize;

    /** Pointer to the data for the memory access. */
    uint8_t *memData = nullptr;

    /** Load queue index. */
    ssize_t lqIdx = -1;
    typename LSQUnit::LQIterator lqIt;

    /** Store queue index. */
    ssize_t sqIdx = -1;
    typename LSQUnit::SQIterator sqIt;

    /** If load data is from cache then it must be golden */
    uint8_t goldenData[8] = {0};

    int pf_source  = -1; // if load cache line is prefetched
    /////////////////////// TLB Miss //////////////////////
    /**
     * Saved memory request (needed when the DTB address translation is
     * delayed due to a hw page table walk).
     */
    LSQ::LSQRequest *savedRequest = nullptr;

    /**
     * Saved Cache miss memory request
     */
    LSQ::LSQRequest *pendingCacheReq = nullptr;

    /////////////////////// Checker //////////////////////
    // Need a copy of main request pointer to verify on writes.
    RequestPtr reqToVerify;

    IssueQue* issueQue = nullptr;
    int issueportid = -1;
    int iqtag = -1;

  public:
    /** Records changes to result? */
    void recordResult(bool f) { instFlags[RecordResult] = f; }

    /** Is the locked write success */
    bool lockedWriteSuccess() const { return instFlags[LockedWriteSuccess]; }
    void lockedWriteSuccess(bool b) { instFlags[LockedWriteSuccess] = b; }

    /** Is the effective virtual address valid. */
    bool effAddrValid() const { return instFlags[EffAddrValid]; }
    void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }

    /** Whether or not the memory operation is done. */
    bool memOpDone() const { return instFlags[MemOpDone]; }
    void memOpDone(bool f) { instFlags[MemOpDone] = f; }

    bool notAnInst() const { return instFlags[NotAnInst]; }
    void setNotAnInst() { instFlags[NotAnInst] = true; }

    void setEmptyMov() { instFlags[IsEmptyMov] = true; }

    void setConstantFolded() { instFlags[IsConstantFolded] = true; }

    ////////////////////////////////////////////
    //
    // INSTRUCTION EXECUTION
    //
    ////////////////////////////////////////////

    void
    demapPage(Addr vaddr, uint64_t asn) override
    {
        cpu->demapPage(vaddr, asn);
    }

    Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
            const std::vector<bool> &byte_enable) override;

    Fault initiateMemMgmtCmd(Request::Flags flags) override;

    Fault writeMem(uint8_t *data, unsigned size, Addr addr,
                   Request::Flags flags, uint64_t *res,
                   const std::vector<bool> &byte_enable) override;

    Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
                         AtomicOpFunctorPtr amo_op) override;

    /** True if the DTB address translation has started. */
    bool translationStarted() const { return instFlags[TranslationStarted]; }
    void translationStarted(bool f) { instFlags[TranslationStarted] = f; }

    /** True if the DTB address translation has completed. */
    bool
    translationCompleted() const
    {
        return instFlags[TranslationCompleted];
    }
    void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }


    void setNormalLd(bool t) { instFlags[NormalLd] = t; }

    bool isNormalLd() const
    {
        return instFlags[NormalLd];
    }

    /** True if this address was found to match a previous load and they issued
     * out of order. If that happend, then it's only a problem if an incoming
     * snoop invalidate modifies the line, in which case we need to squash.
     * If nothing modified the line the order doesn't matter.
     */
    bool
    possibleLoadViolation() const
    {
        return instFlags[PossibleLoadViolation];
    }
    void
    possibleLoadViolation(bool f)
    {
        instFlags[PossibleLoadViolation] = f;
    }

    /** True if the address hit a external snoop while sitting in the LSQ.
     * If this is true and a older instruction sees it, this instruction must
     * reexecute
     */
    bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
    void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }

    /**
     * Returns true if the DTB address translation is being delayed due to a hw
     * page table walk.
     */
    bool
    isTranslationDelayed() const
    {
        return (translationStarted() && !translationCompleted());
    }

  public:
#ifdef DEBUG
    void dumpSNList();
#endif


    int32_t operWid() const { return staticInst->operWid(); }

    /** Renames a destination register to a physical register.  Also records
     *  the previous physical register that the logical register mapped to.
     */
    void
    renameDestReg(int idx, VirtRegId renamed_dest,
                  VirtRegId previous_rename)
    {
        renamedDestIdx(idx, renamed_dest);
        prevDestIdx(idx, previous_rename);
        if (renamed_dest.PhyReg()->isPinned())
            setPinnedRegsRenamed();
    }

    /** Renames a source logical register to the physical register which
     *  has/will produce that logical register's result.
     *  @todo: add in whether or not the source register is ready.
     */
    void
    renameSrcReg(int idx, VirtRegId renamed_src)
    {
        renamedSrcIdx(idx, renamed_src);
    }

    bool isDependentOn(const DynInstPtr &other) const;

    /** Dumps out contents of this BaseDynInst. */
    void dump();

    /** Dumps out contents of this BaseDynInst into given string. */
    void dump(std::string &outstring);

    /** Read this CPU's ID. */
    int cpuId() const { return cpu->cpuId(); }

    /** Read this CPU's Socket ID. */
    uint32_t socketId() const { return cpu->socketId(); }

    /** Read this CPU's data requestor ID */
    RequestorID requestorId() const { return cpu->dataRequestorId(); }

    /** Read this context's system-wide ID **/
    ContextID contextId() const { return thread->contextId(); }

    /** Returns the fault type. */
    Fault getFault() const { return fault; }
    /** TODO: This I added for the LSQRequest side to be able to modify the
     * fault. There should be a better mechanism in place. */
    Fault& getFault() { return fault; }

    bool faulted() const { return fault != NoFault; }

    /** Checks whether or not this instruction has had its branch target
     *  calculated yet.  For now it is not utilized and is hacked to be
     *  always false.
     *  @todo: Actually use this instruction.
     */
    bool doneTargCalc() { return false; }

    /** Set the predicted target of this current instruction. */
    void setPredTarg(const PCStateBase &pred_pc) { set(predPC, pred_pc); }

    const PCStateBase &readPredTarg() { return *predPC; }

    /** Returns whether the instruction was predicted taken or not. */
    bool readPredTaken() { return instFlags[PredTaken]; }

    void
    setPredTaken(bool predicted_taken)
    {
        instFlags[PredTaken] = predicted_taken;
    }

    // ---- Trace branch/control-flow ground-truth (used by Decode/EXE in trace mode)
    bool traceBranchInfoValid = false;
    bool traceBranchTakenValue = false;
    bool traceBranchHasTargetValue = false;
    Addr traceBranchTargetValue = 0;
    Addr traceBranchNextPCValue = 0;
    // trace 侧标记该指令是否触发非普通顺序的控制流改变（例如 trap/异常）。
    bool traceCtrlFlowChangeValue = false;
    bool traceIsCallValue = false;
    bool traceIsReturnValue = false;
    bool traceIsIndirectValue = false;

    void clearTraceBranchInfo()
    {
        traceBranchInfoValid = false;
        traceBranchTakenValue = false;
        traceBranchHasTargetValue = false;
        traceBranchTargetValue = 0;
        traceBranchNextPCValue = 0;
        traceCtrlFlowChangeValue = false;
        traceIsCallValue = false;
        traceIsReturnValue = false;
        traceIsIndirectValue = false;
    }

    void setTraceBranchInfo(bool taken, bool hasTarget, Addr branchTarget,
                            Addr fallthrough)
    {
        traceBranchInfoValid = true;
        traceBranchTakenValue = taken;
        traceBranchHasTargetValue = hasTarget;
        traceBranchTargetValue = hasTarget ? branchTarget : 0;
        traceBranchNextPCValue = taken ?
            (hasTarget ? branchTarget : fallthrough) :
            fallthrough;
    }

    void setTraceCtrlFlowChange(bool hasCtrlFlowChange)
    {
        traceCtrlFlowChangeValue = hasCtrlFlowChange;
    }
    void setTraceIsCall(bool v) { traceIsCallValue = v; }
    void setTraceIsReturn(bool v) { traceIsReturnValue = v; }
    void setTraceIsIndirect(bool v) { traceIsIndirectValue = v; }

    bool hasTraceBranchInfo() const { return traceBranchInfoValid; }
    bool traceBranchTaken() const { return traceBranchInfoValid && traceBranchTakenValue; }
    bool traceBranchHasTarget() const { return traceBranchInfoValid && traceBranchHasTargetValue; }
    Addr traceBranchTarget() const { return traceBranchHasTargetValue ? traceBranchTargetValue : 0; }
    Addr traceBranchNextPC() const { return traceBranchInfoValid ? traceBranchNextPCValue : 0; }
    bool hasTraceCtrlFlowChange() const { return traceCtrlFlowChangeValue; }
    bool traceIsCall() const { return traceIsCallValue; }
    bool traceIsReturn() const { return traceIsReturnValue; }
    bool traceIsIndirect() const { return traceIsIndirectValue; }

    // 标记并查询该动态指令是否对应 trace 流中的最后一条，用于
    // 在 commit 阶段识别“最后一条 trace 指令已提交”，实现自然退出。
    void setLastTraceInst(bool v) { lastTraceInstFlag = v; }
    bool isLastTraceInst() const { return lastTraceInstFlag; }

    /** Returns whether the instruction mispredicted. */
    bool
    mispredicted()
    {
        std::unique_ptr<PCStateBase> next_pc(pc->clone());
        staticInst->advancePC(*next_pc);
        DPRINTF(DecoupleBP, "check misprediction next pc=%s and pred pc=%s\n",
                *next_pc, *predPC);
        return *next_pc != *predPC;
    }

    //
    //  Instruction types.  Forward checks to StaticInst object.
    //
    bool isSplitStoreAddr()   const { return staticInst->isSplitStoreAddr(); }
    bool isSplitStoreData() const { return opClass() == StoreDataOp; }
    bool isFusion()       const { return staticInst->isFusion(); }
    bool isNop()          const { return staticInst->isNop(); }
    bool isMemRef()       const { return staticInst->isMemRef(); }
    bool isLoad()         const { return staticInst->isLoad(); }
    bool isHInst()        const { return staticInst->isHInst(); }
    bool isStore()        const { return staticInst->isStore(); }
    bool isAtomic()       const { return staticInst->isAtomic(); }
    bool isStoreConditional() const
    { return staticInst->isStoreConditional(); }
    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
    bool isInteger()      const { return staticInst->isInteger(); }
    bool isFloating()     const { return staticInst->isFloating(); }
    bool isVector()       const { return staticInst->isVector(); }
    bool isControl()      const { return staticInst->isControl(); }
    bool isCall()         const { return staticInst->isCall(); }
    bool isReturn()       const { return staticInst->isReturn(); }
    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
    bool isSerializing()  const { return staticInst->isSerializing(); }
    bool isMov()          const { return staticInst->isMov(); }
    bool isAddImm()       const { return staticInst->isAddImm(); }
    bool isEliminated() const
    {
        return instFlags[IsEmptyMov] || instFlags[IsConstantFolded];
    }
    bool
    isSerializeBefore() const
    {
        return staticInst->isSerializeBefore() || status[SerializeBefore];
    }
    bool
    isSerializeAfter() const
    {
        return staticInst->isSerializeAfter() || status[SerializeAfter];
    }
    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
    bool isFullMemBarrier()   const { return staticInst->isFullMemBarrier(); }
    bool isReadBarrier() const { return staticInst->isReadBarrier(); }
    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
    bool isUpdateVsstatusSd() const {return staticInst->isUpdateVsstatusSd(); }
    bool isUpdateMstatusSd() const {return staticInst->isUpdateMstatusSd(); }
    bool isQuiesce() const { return staticInst->isQuiesce(); }
    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
    bool isSyscall() const { return staticInst->isSyscall(); }
    bool isMacroop() const { return staticInst->isMacroop(); }
    bool isMicroop() const { return staticInst->isMicroop(); }
    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
    // hardware transactional memory
    bool isHtmStart() const { return staticInst->isHtmStart(); }
    bool isHtmStop() const { return staticInst->isHtmStop(); }
    bool isHtmCancel() const { return staticInst->isHtmCancel(); }
    bool isHtmCmd() const { return staticInst->isHtmCmd(); }

    uint64_t
    getHtmTransactionUid() const override
    {
        assert(instFlags[HtmFromTransaction]);
        return htmUid;
    }

    uint64_t
    newHtmTransactionUid() const override
    {
        panic("Not yet implemented\n");
        return 0;
    }

    bool
    inHtmTransactionalState() const override
    {
        return instFlags[HtmFromTransaction];
    }

    uint64_t
    getHtmTransactionalDepth() const override
    {
        if (inHtmTransactionalState())
            return htmDepth;
        else
            return 0;
    }

    void
    setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
    {
        instFlags.set(HtmFromTransaction);
        htmUid = htm_uid;
        htmDepth = htm_depth;
    }

    void
    clearHtmTransactionalState()
    {
        if (inHtmTransactionalState()) {
            DPRINTF(HtmCpu,
                "clearing instuction's transactional state htmUid=%u\n",
                getHtmTransactionUid());

            instFlags.reset(HtmFromTransaction);
            htmUid = -1;
            htmDepth = 0;
        }
    }

    /** Temporarily sets this instruction as a serialize before instruction. */
    void setSerializeBefore() { status.set(SerializeBefore); }

    /** Clears the serializeBefore part of this instruction. */
    void clearSerializeBefore() { status.reset(SerializeBefore); }

    /** Checks if this serializeBefore is only temporarily set. */
    bool isTempSerializeBefore() { return status[SerializeBefore]; }

    /** Temporarily sets this instruction as a serialize after instruction. */
    void setSerializeAfter() { status.set(SerializeAfter); }

    /** Clears the serializeAfter part of this instruction.*/
    void clearSerializeAfter() { status.reset(SerializeAfter); }

    /** Checks if this serializeAfter is only temporarily set. */
    bool isTempSerializeAfter() { return status[SerializeAfter]; }

    /** Sets the serialization part of this instruction as handled. */
    void setSerializeHandled() { status.set(SerializeHandled); }

    /** Checks if the serialization part of this instruction has been
     *  handled.  This does not apply to the temporary serializing
     *  state; it only applies to this instruction's own permanent
     *  serializing state.
     */
    bool isSerializeHandled() { return status[SerializeHandled]; }

    /** Returns the opclass of this instruction. */
    OpClass opClass() const { return staticInst->opClass(); }

    /** Returns the branch target address. */
    std::unique_ptr<PCStateBase>
    branchTarget() const
    {
        if (traceBranchHasTarget()) {
            // Construct a concrete PCState for the current ISA to hold the
            // absolute target address, then return it as PCStateBase.
            return std::make_unique<TheISA::PCState>(traceBranchTarget());
        } else {
            return staticInst->branchTarget(*pc);
        }
    }

    /** Returns the number of source registers. */
    size_t numSrcRegs() const { return numSrcs(); }

    /** Returns the number of destination registers. */
    size_t numDestRegs() const { return numDests(); }

    size_t
    numDestRegs(RegClassType type) const
    {
        return staticInst->numDestRegs(type);
    }

    /** Returns the logical register index of the i'th destination register. */
    const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }

    /** Returns the logical register index of the i'th source register. */
    const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }

    uint64_t getAmoOldGoldenValue() const { return amoOldGoldenValue; }

    void *getAmoOldGoldenValuePtr() { return (void *) &amoOldGoldenValue; }

    /** Return the size of the instResult queue. */
    uint8_t resultSize() { return instResult.size(); }

    /** Pops a result off the instResult queue.
     * If the result stack is empty, return the default value.
     * */
    InstResult
    popResult(InstResult dflt=InstResult())
    {
        if (!instResult.empty()) {
            InstResult t = instResult.front();
            instResult.pop();
            return t;
        }
        return dflt;
    }

    InstResult getResult(InstResult dflt = InstResult())
    {
        if (!instResult.empty()) {
            InstResult t = instResult.front();
            return t;
        }
        return dflt;
    }

    /** Pushes a result onto the instResult queue. */
    /** @{ */
    template<typename T>
    void
    setResult(T &&t)
    {
        if (instFlags[RecordResult]) {
            instResult.emplace(std::forward<T>(t));
        }
    }
    /** @} */

    /** Records that one of the source registers is ready. */
    void markSrcRegReady();

    /** Marks a specific register as ready. */
    void markSrcRegReady(RegIndex src_idx);

    void clearSrcRegReady(RegIndex src_idx);

    uint8_t getNumSrcRegReady() { return readyRegs; }

    void resetNumSrcRegReady(uint8_t n);

    /** Sets this instruction as completed. */
    void setCompleted() { status.set(Completed); }

    /** Returns whether or not this instruction is completed. */
    bool isCompleted() const { return status[Completed]; }

    /** Marks the result as ready. */
    void setResultReady() { status.set(ResultReady); }

    /** Returns whether or not the result is ready. */
    bool isResultReady() const { return status[ResultReady]; }

    /** Sets this instruction as ready to issue. */
    void setCanIssue() { status.set(CanIssue); }

    /** Returns whether or not this instruction is ready to issue. */
    bool readyToIssue() const { return status[CanIssue]; }

    /** Clears this instruction being able to issue. */
    void clearCanIssue() { status.reset(CanIssue); }

    // mem only, dependencies was solved
    void setMemDepDone() { status.set(MemDepSolved); }

    bool memDepSolved() const { return status[MemDepSolved]; }

    void setWriteback() { issueQue = nullptr; issueportid = -1; }

    /** Scheduler state begin */

    void setInReadyQ() { status.set(InReadyQue); }

    // leave readyQ and already to schedule
    void clearInReadyQ() { status.reset(InReadyQue); }

    bool inReadyQ() const { return status[InReadyQue]; }

    // cancled
    void setCancel() { status.set(Canceled); }

    void clearCancel() { status.reset(Canceled); }

    bool canceled() const { return status[Canceled]; }

    void setScheduled() { status.set(Scheduled); }

    void clearScheduled() { status.reset(Scheduled); }

    bool isScheduled() const { return status[Scheduled]; }

    // schedule failed
    void setArbFailed() { status.set(ArbFailed); }

    void clearArbFailed() { status.reset(ArbFailed); }

    bool arbFailed() const { return status[ArbFailed]; }

    /** leave issueStage and goto FuncUnits */
    void setIssued() { status.set(Issued); }

    bool isIssued() const { return status[Issued]; }

    /** Scheduler state end */


    /** load/store pipe state begin */

    void beginPipelining() {
                status &= ~(
                    (1 << CacheHit) |
                    (1 << WakeUpEarly) |
                    (1 << FullForward) |
                    (1 << LocalAccess) |
                    (1 << NeedReplay) |
                    (1 << SkipFollowingPipe));
        status.set(InPipe);
        clearReplayType();
    }

    void endPipelining() {
        status.reset(InPipe);
    }

    bool inPipe() const { return status[InPipe]; }

    void setCacheHit() { status.set(CacheHit); }
    bool cacheHit() const { return status[CacheHit]; }

    void setReplay(LdStReplayType type) {
        setNeedReplay();
        replayType = type;
    }
    std::optional<LdStReplayType> getReplayType() const {
        return replayType;
    }
    void clearReplayType() { replayType.reset(); }

    // only can be set once!!!
    void setNeedReplay() {
        assert(!status[NeedReplay]);
        status.set(NeedReplay);
    }
    bool needReplay() const { return status[NeedReplay]; }

    void setTLBMissReplay() { setReplay(LdStReplayType::TLBMissReplay); }
    bool needTLBMissReplay() const { return getReplayType() == LdStReplayType::TLBMissReplay; }

    void setCacheMissReplay() { setReplay(LdStReplayType::CacheMissReplay); }
    bool needCacheMissReplay() const { return getReplayType() == LdStReplayType::CacheMissReplay; }

    void setRescheduleReplay() { setReplay(LdStReplayType::RescheduleReplay); }
    bool needRescheduleReplay() const { return getReplayType() == LdStReplayType::RescheduleReplay; }

    void setSTLFReplay() { setReplay(LdStReplayType::STLFReplay); }
    bool needSTLFReplay() const { return getReplayType() == LdStReplayType::STLFReplay; }

    void setNukeReplay() { setReplay(LdStReplayType::NukeReplay); }
    bool needNukeReplay() const { return getReplayType() == LdStReplayType::NukeReplay; }

    void setCacheBlockedReplay() { setReplay(LdStReplayType::CacheBlockedReplay); }
    bool needCacheBlockedReplay() const { return getReplayType() == LdStReplayType::CacheBlockedReplay; }

    void setBankConflictReplay() { setReplay(LdStReplayType::BankConflictReplay); }
    bool needBankConflictReplay() const { return getReplayType() == LdStReplayType::BankConflictReplay; }

    // MSHR Replay
    void setMshrArbFailReplay() { setReplay(LdStReplayType::MshrArbFailReplay); }
    bool needMshrArbFailReplay() const { return getReplayType() == LdStReplayType::MshrArbFailReplay; }

    void setRARReplay() { setReplay(LdStReplayType::RARReplay); }
    bool needRARReplay() const { return getReplayType() == LdStReplayType::RARReplay; }

    void setRAWReplay() { setReplay(LdStReplayType::RAWReplay); }
    bool needRAWReplay() const { return getReplayType() == LdStReplayType::RAWReplay; }

    void clearNeedReplay() { status.reset(NeedReplay); }
    void setMshrAliasFailReplay() { setReplay(LdStReplayType::MshrAliasFailReplay); }
    bool needMshrAliasFailReplay() const { return getReplayType() == LdStReplayType::MshrAliasFailReplay; }

    void setHitInWriteBufferReplay() { setReplay(LdStReplayType::HitInWriteBufferReplay); }
    bool needHitInWriteBufferReplay() const { return getReplayType() == LdStReplayType::HitInWriteBufferReplay; }

    void setFullForward() { status.set(FullForward); }
    bool fullForward() const { return status[FullForward]; }

    void setWakeUpEarly() { status.set(WakeUpEarly); }
    bool wakeUpEarly() const { return status[WakeUpEarly]; }

    void setSkipFollowingPipe() { status.set(SkipFollowingPipe); }
    bool replayOrSkipFollowingPipe() const { return status[SkipFollowingPipe] || status[NeedReplay]; }

    void setSkipRawCheck() { status.set(SkipRawCheck); }
    void clearSkipRawCheck() { status.reset(SkipRawCheck); }
    bool skipRawCheck() const { return status[SkipRawCheck]; }

    /** True if inst is waiting for Dcache refill. */
    bool waitingCacheRefill() const { return instFlags[WaitingCacheRefill]; }
    void setWaitingCacheRefill() { instFlags.set(WaitingCacheRefill); }
    void clearWaitingCacheRefill() { instFlags.reset(WaitingCacheRefill); }

    void waitingCacheRefill(bool f) { instFlags[WaitingCacheRefill] = f; }

    /** True if inst is has pending cache request. */
    bool hasPendingCacheReq() const { return instFlags[HasPendingCacheReq]; }
    void hasPendingCacheReq(bool f) { instFlags[HasPendingCacheReq] = f; }

    /** load/store pipe state end */

    /** Sets this instruction as executed. */
    void setExecuted() { status.set(Executed); }

    /** Returns whether or not this instruction has executed. */
    bool isExecuted() const { return status[Executed]; }

    /** Sets this instruction as ready to commit. */
    void setCanCommit() { status.set(CanCommit); }

    /** Clears this instruction as being ready to commit. */
    void clearCanCommit() { status.reset(CanCommit); }

    /** Returns whether or not this instruction is ready to commit. */
    bool readyToCommit() const { return status[CanCommit]; }

    void setAtCommit() { status.set(AtCommit); }

    bool isAtCommit() { return status[AtCommit]; }

    /** Sets this instruction as committed. */
    void setCommitted() { status.set(Committed); }

    /** Returns whether or not this instruction is committed. */
    bool isCommitted() const { return status[Committed]; }

    /** Sets this instruction as squashed. */
    void setSquashed();

    /** Returns whether or not this instruction is squashed. */
    bool isSquashed() const { return status[Squashed]; }

    /** Sets this instruction as squashed in the IQ. */
    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}

    /** Returns whether or not this instruction is squashed in the IQ. */
    bool isSquashedInIQ() const { return status[SquashedInIQ]; }


    //Load / Store Queue Functions
    //-----------------------
    /** Sets this instruction as a entry the LSQ. */
    void setInLSQ() { status.set(LsqEntry); }

    /** Sets this instruction as a entry the LSQ. */
    void removeInLSQ() { status.reset(LsqEntry); }

    /** Returns whether or not this instruction is in the LSQ. */
    bool isInLSQ() const { return status[LsqEntry]; }

    /** Sets this instruction as squashed in the LSQ. */
    void setSquashedInLSQ() { status.set(SquashedInLSQ); status.set(Squashed);}

    /** Returns whether or not this instruction is squashed in the LSQ. */
    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }


    //Reorder Buffer Functions
    //-----------------------
    /** Sets this instruction as a entry the ROB. */
    void setInROB() { status.set(RobEntry); }

    /** Sets this instruction as a entry the ROB. */
    void clearInROB() { status.reset(RobEntry); }

    /** Returns whether or not this instruction is in the ROB. */
    bool isInROB() const { return status[RobEntry]; }

    /** Sets this instruction as squashed in the ROB. */
    void setSquashedInROB() { status.set(SquashedInROB); }

    /** Returns whether or not this instruction is squashed in the ROB. */
    bool isSquashedInROB() const { return status[SquashedInROB]; }

    /** Returns whether pinned registers are renamed */
    bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }

    /** Sets the destination registers as renamed */
    void
    setPinnedRegsRenamed()
    {
        assert(!status[PinnedRegsSquashDone]);
        assert(!status[PinnedRegsWritten]);
        status.set(PinnedRegsRenamed);
    }

    /** Returns whether destination registers are written */
    bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }

    /** Sets destination registers as written */
    void
    setPinnedRegsWritten()
    {
        assert(!status[PinnedRegsSquashDone]);
        assert(status[PinnedRegsRenamed]);
        status.set(PinnedRegsWritten);
    }

    /** Return whether dest registers' pinning status updated after squash */
    bool
    isPinnedRegsSquashDone() const
    {
        return status[PinnedRegsSquashDone];
    }

    /** Sets dest registers' status updated after squash */
    void
    setPinnedRegsSquashDone()
    {
        assert(!status[PinnedRegsSquashDone]);
        status.set(PinnedRegsSquashDone);
    }

    /** Read the PC state of this instruction. */
    const PCStateBase &
    pcState() const override
    {
        return *pc;
    }

    /** Set the PC state of this instruction. */
    void pcState(const PCStateBase &val) override { set(pc, val); }

    bool readPredicate() const override { return instFlags[Predicate]; }

    void
    setPredicate(bool val) override
    {
        instFlags[Predicate] = val;

        if (traceData) {
            traceData->setPredicate(val);
        }
    }

    bool
    readMemAccPredicate() const override
    {
        return instFlags[MemAccPredicate];
    }

    void
    setMemAccPredicate(bool val) override
    {
        instFlags[MemAccPredicate] = val;
    }

    /** Sets the thread id. */
    void setTid(ThreadID tid) { threadNumber = tid; }

    /** Sets the pointer to the thread state. */
    void setThreadState(ThreadState *state) { thread = state; }

    /** Returns the thread context. */
    gem5::ThreadContext *tcBase() const override { return thread->getTC(); }

  public:
    /** Is this instruction's memory access strictly ordered? */
    bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
    void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }

    /** Has this instruction generated a memory request. */
    bool hasRequest() const { return instFlags[ReqMade]; }
    /** Assert this instruction has generated a memory request. */
    void setRequest() { instFlags[ReqMade] = true; }

    /** Returns iterator to this instruction in the list of all insts. */
    ListIt &getInstListIt() { return instListIt; }

    /** Sets iterator for this instruction in the list of all insts. */
    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }

  public:


    /** Returns the number of consecutive store conditional failures. */
    unsigned int
    readStCondFailures() const override
    {
        return thread->storeCondFailures;
    }

    /** Sets the number of consecutive store conditional failures. */
    void
    setStCondFailures(unsigned int sc_failures) override
    {
        thread->storeCondFailures = sc_failures;
    }

  public:
    // monitor/mwait funtions
    void
    armMonitor(Addr address) override
    {
        cpu->armMonitor(threadNumber, address);
    }
    bool
    mwait(PacketPtr pkt) override
    {
        return cpu->mwait(threadNumber, pkt);
    }
    void
    mwaitAtomic(gem5::ThreadContext *tc) override
    {
        return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
    }
    AddressMonitor *
    getAddrMonitor() override
    {
        return cpu->getCpuAddrMonitor(threadNumber);
    }

  private:
    // hardware transactional memory
    uint64_t htmUid = -1;
    uint64_t htmDepth = 0;

  public:
#if TRACING_ON
    // Value -1 indicates that particular phase
    // hasn't happened (yet).
    /** Tick records used for the pipeline activity viewer. */
    Tick fetchTick = -1;      // instruction fetch is completed.
    int32_t decodeTick = -1;  // instruction enters decode phase
    int32_t renameTick = -1;  // instruction enters rename phase
    int32_t dispatchTick = -1;
    int32_t issueTick = -1;
    int32_t completeTick = -1;
    int32_t commitTick = -1;
    int32_t storeTick = -1;
#endif

    /* Values used by LoadToUse stat */
    Tick enterDQTick = -1;
    Tick exitDQTick = -1;
    Tick firstIssue = -1;
    Tick lastWakeDependents = -1;
    Tick translatedTick = -1;

    Tick readyTick = -1;
    Tick completionTick = -1;

    /** RAR/RAW replay queue entry timestamps for latency calculation */
    Tick RARQueueEntryTick = -1;
    Tick RAWQueueEntryTick = -1;

    /** Reads a misc. register, including any side-effects the read
     * might have as defined by the architecture.
     */
    RegVal
    readMiscReg(int misc_reg) override
    {
        return cpu->readMiscReg(misc_reg, threadNumber);
    }

    /** Sets a misc. register, including any side-effects the write
     * might have as defined by the architecture.
     */
    void
    setMiscReg(int misc_reg, RegVal val) override
    {
        /** Writes to misc. registers are recorded and deferred until the
         * commit stage, when updateMiscRegs() is called. First, check if
         * the misc reg has been written before and update its value to be
         * committed instead of making a new entry. If not, make a new
         * entry and record the write.
         */
        for (auto &idx: _destMiscRegIdx) {
            if (idx == misc_reg)
                return;
        }

        DPRINTF(RiscvMisc, "Push misc reg %i: %#lx\n", misc_reg, val);
        _destMiscRegIdx.push_back(misc_reg);
        _destMiscRegVal.push_back(val);
    }

    /** Reads a misc. register, including any side-effects the read
     * might have as defined by the architecture.
     */
    RegVal
    readMiscRegOperand(const StaticInst *si, int idx) override
    {
        const RegId& reg = si->srcRegIdx(idx);
        assert(reg.is(MiscRegClass));
        return cpu->readMiscReg(reg.index(), threadNumber);
    }

    /** Sets a misc. register, including any side-effects the write
     * might have as defined by the architecture.
     */
    void
    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
    {
        const RegId& reg = si->destRegIdx(idx);
        assert(reg.is(MiscRegClass));
        setMiscReg(reg.index(), val);
    }

    /** Called at the commit stage to update the misc. registers. */
    void
    updateMiscRegs()
    {
        // @todo: Pretty convoluted way to avoid squashing from happening when
        // using the TC during an instruction's execution (specifically for
        // instructions that have side-effects that use the TC).  Fix this.
        // See cpu/o3/dyn_inst_impl.hh.
        bool no_squash_from_TC = thread->noSquashFromTC;
        thread->noSquashFromTC = true;

        for (int i = 0; i < _destMiscRegIdx.size(); i++)
            cpu->setMiscReg(
                _destMiscRegIdx[i], _destMiscRegVal[i], threadNumber);

        thread->noSquashFromTC = no_squash_from_TC;
    }

    void
    forwardOldRegs()
    {

        for (int idx = 0; idx < numDestRegs(); idx++) {
            VirtRegId prev_phys_reg = prevDestIdx(idx);
            const RegId& original_dest_reg = staticInst->destRegIdx(idx);
            switch (original_dest_reg.classValue()) {
              case IntRegClass:
              case FloatRegClass:
              case CCRegClass:
              case RMiscRegClass:
                setRegOperand(staticInst.get(), idx,
                        cpu->getReg(prev_phys_reg));
                break;
              case VecRegClass:
                {
                    TheISA::VecRegContainer val;
                    cpu->getReg(prev_phys_reg.PhyReg(), &val);
                    setRegOperand(staticInst.get(), idx, &val);
                }
                break;
              case VecElemClass:
                setRegOperand(staticInst.get(), idx,
                        cpu->getReg(prev_phys_reg));
                break;
              case VecPredRegClass:
                {
                    TheISA::VecPredRegContainer val;
                    cpu->getReg(prev_phys_reg.PhyReg(), &val);
                    setRegOperand(staticInst.get(), idx, &val);
                }
                break;
              case InvalidRegClass:
              case MiscRegClass:
                // no need to forward misc reg values
                break;
              default:
                panic("Unknown register class: %d",
                        (int)original_dest_reg.classValue());
            }
        }
    }
    /** Traps to handle specified fault. */
    void trap(const Fault &fault);

  public:

    // The register accessor methods provide the index of the
    // instruction's operand (e.g., 0 or 1), not the architectural
    // register index, to simplify the implementation of register
    // renaming.  We find the architectural register index by indexing
    // into the instruction's own operand index table.  Note that a
    // raw pointer to the StaticInst is provided instead of a
    // ref-counted StaticInstPtr to redice overhead.  This is fine as
    // long as these methods don't copy the pointer into any long-term
    // storage (which is pretty hard to imagine they would have reason
    // to do).

    RegVal
    getRegOperand(const StaticInst *si, int idx) override
    {
        const VirtRegId reg = extRenamedSrcIdx(idx);
        return cpu->getReg(reg);
    }

    void
    getRegOperand(const StaticInst *si, int idx, void *val) override
    {
        const VirtRegId reg = extRenamedSrcIdx(idx);
        if (reg.PhyReg()->is(InvalidRegClass))
            return;
        cpu->getReg(reg.PhyReg(), val);
    }

    void *
    getWritableRegOperand(const StaticInst *si, int idx) override
    {
        return cpu->getWritableReg(extRenamedDestIdx(idx).PhyReg());
    }

    /** @todo: Make results into arrays so they can handle multiple dest
     *  registers.
     */
    void
    setRegOperand(const StaticInst *si, int idx, RegVal val) override
    {
        const PhysRegIdPtr reg = extRenamedDestIdx(idx).PhyReg();
        if (reg->is(InvalidRegClass))
            return;
        cpu->setReg(reg, val);
        setResult(val);
    }

    void
    setRegOperand(const StaticInst *si, int idx, const void *val) override
    {
        const PhysRegIdPtr reg = extRenamedDestIdx(idx).PhyReg();
        if (reg->is(InvalidRegClass))
            return;
        cpu->setReg(reg, val);
        //TODO setResult
    }

    void printDisassemblyAndResult(const std::string &site) const;

    std::string genDisassembly() const
    {
        std::string str = "";
        str += csprintf("[sn:%lu pc:%#lx] %s",
                seqNum, pcState().instAddr(),
                staticInst->disassemble(pcState().instAddr()));
        if (instResult.size() > 0) {
            str += csprintf(", res: %#lx", instResult.front().as<uint64_t>());
        }
        else if (numDestRegs() > 0 && isVector()) {
            uint64_t val[RiscvISA::NumVecElemPerVecReg];
            cpu->getArchReg(destRegIdx(0), val, threadNumber);
            std::string s_val;
            for (int j=RiscvISA::NumVecElemPerVecReg-1; j>=0; j--) {
                s_val += csprintf("%016lx", val[j]);
                if (j != 0) {
                    s_val+="_";
                }
            }
            str += csprintf(", res: %s", s_val);
        }
        if (isMemRef()) {
            str += csprintf(", paddr: %#lx", physEffAddr);
        }
        return str;
    }


    void
    setFtqId(unsigned id)
    {
        ftqId = id;
    }

    unsigned
    getFtqId()
    {
        return ftqId;
    }

    void
    setLoopIteration(unsigned iter)
    {
        loopIteration = iter;
    }

    unsigned
    getLoopIteration()
    {
        return loopIteration;
    }

    unsigned getInstBytes()
    {
        RiscvISA::PCState rpc = pc->as<RiscvISA::PCState>();
        return rpc.compressed() ? 2 : 4;
    }

  protected:
    SquashVersion squashVer;

  public:
    void setVersion(const SquashVersion &ver)
    {
        squashVer.update(ver.getVersion());
    }
    uint8_t getVersion()
    {
        return squashVer.getVersion();
    }

    ssize_t getLqIdx()
    {
        return lqIdx;
    }

    Addr getPC()
    {
        return pc->instAddr();
    }

    Addr getNPC()
    {
        return pc->as<RiscvISA::PCState>().npc();
    }

    bool branching()
    {
        return pc->as<RiscvISA::PCState>().branching();
    }

    /** set golden */
    void setGolden(uint8_t *golden) { memcpy(goldenData, golden, effSize); }

    /** get golden */
    uint8_t *getGolden() { return goldenData; }
};

} // namespace o3
} // namespace gem5

#endif // __CPU_O3_DYN_INST_HH__