timing(CoupledL2): optimize timing#503
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…rs related to multi-cycle-path
When a way is occupied by mshr, it must be hit, or chosen as refill way in mainpipe stage 3, which means it is definitely not invalid. On the other hand, a selected invalid replace way must be a freeWay. So don't use invalidWay to lookup freeWayMask when choose replace way.
After reset, the first access to a certain way will inevitably be selected as invalid way, and the read value from the replacer SRAM and origin bit SRAM won't be used at this time. At the same time, these SRAMs are written after selection, which is equivalent to initializing them. Therefore, the initialization of these SRAMs can be removed.
For hit related logic, it won't use meta chosen by replace logic, so does replace related logic. So decouple them.
Connection of source_req_s3 and status_vec_toTX will generate a path from replace logic to TX Module, which causes critical path. So just use task_s3 as status_vec_toTX[0]. This may cause a decrease performance of snoop.
Passing origin bit sram read by HoldUless will cause critical path from origin bit sram read resp port to origin bit sram write port. So use RegEnable to pass it.
When receiving aMergeTask during mshr task fire, mshr should immediatly pass aMergeTask ti mshr_tasj_arb, causing direct connection from TLBuffer --> SinkA --> reqBuffer --> mshr --> mshrCtl/arb. So dong't merge aMergeTask when mshr_task is going to fire.
Current cmo logic will use result from replace logic by using dirReault.meta. So decouple replace logic and cmo logic.
Current nestable_meta of snoop will use the result from replace logic by using dirResult.meta. So decouple them.
Current prefetch train will use the meta from replace logic. So decouple them.
Some input value of arbiter in bop is he same constant value. So assign these value in output directly.
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move TwoLevelRRArbiter and MaskToOH to utility and bump
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