fix(RequestArb): inequal fire condition for RequestBuf and MainPipe on s1

Author: Kumonda221-CrO3

src/main/scala/coupledL2/RequestArb.scala

@@ -175,7 +175,7 @@ class RequestArb(implicit p: Parameters) extends L2Module
   val s1_to_s2_valid = Wire(Bool()) 
 
   if (enableCHI)
-    s1_to_s2_valid := task_s1.valid && (!mshr_replRead_stall || task_s1.bits.fromC)
+    s1_to_s2_valid := task_s1.valid && (!mshr_replRead_stall || sinkValids(0))
   else
     s1_to_s2_valid := task_s1.valid && !mshr_replRead_stall