fix(RequestArb): inequal fire condition for RequestBu and MainPipe on s1

Author: Kumonda221-CrO3

src/main/scala/coupledL2/RequestArb.scala

@@ -165,7 +165,7 @@ class RequestArb(implicit p: Parameters) extends L2Module
   chnl_task_s1.bits := ParallelPriorityMux(sinkValids, Seq(C_task, B_task, A_task))
 
   if (enableCHI)
-    chnl_task_s1.valid := (io.sinkC.valid && !mshr_task_s1.valid || io.dirRead_s1.ready) && sinkValids.orR && resetFinish
+    chnl_task_s1.valid := (io.sinkC.fire || io.dirRead_s1.ready) && sinkValids.orR && resetFinish
   else
     chnl_task_s1.valid := io.dirRead_s1.ready && sinkValids.orR && resetFinish