AARCH64: zero-extend dest on ADDV/SMAXV/SMINV/UMAXV/UMINV and FMADD/FMSUB scalar forms#9277
Open
valium007 wants to merge 2 commits into
Open
AARCH64: zero-extend dest on ADDV/SMAXV/SMINV/UMAXV/UMINV and FMADD/FMSUB scalar forms#9277valium007 wants to merge 2 commits into
valium007 wants to merge 2 commits into
Conversation
Across-lane reductions wrote only the result element and left the upper
bits of the destination SIMD&FP register stale, violating the ARM
zero-extension-on-write semantics. Add zext_z{b,h,s} per element size,
and fix ADDV.8B/.16B which used zext_zq (16-byte clear) for an 8-bit
result.
The scalar FMADD and FMSUB constructors (FPR16/FPR32/FPR64) wrote only the result element and left the upper bits of the destination SIMD&FP register unchanged, violating the architectural zero-extension-on-write semantics. The sibling FNMADD/FNMSUB already do this correctly. Add the size-correct zero-extension after each: - FPR16 -> zext_zh - FPR32 -> zext_zs - FPR64 -> zext_zd
valium007
changed the title
ryanmkurtz
added
Feature: Processor/AARCH64
Status: Triage
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Across-lane reductions wrote only the result element and left the upper
bits of the destination SIMD&FP register stale, violating the ARM
zero-extension-on-write semantics. Add zext_z{b,h,s} per element size,
and fix ADDV.8B/.16B which used zext_zq (16-byte clear) for an 8-bit
result. The scalar FMADD and FMSUB constructors (FPR16/FPR32/FPR64) wrote only
the result element and left the upper bits of the destination SIMD&FP
register unchanged, violating the architectural zero-extension-on-write
semantics. The sibling FNMADD/FNMSUB already do this correctly