Mirath in HW

This repository contains the (System)Verilog RTL sources of an efficient HW (FPGA) implementation of Mirath, an MPC-in-the-Head-based post-quantum digital signature algorithm. The design supports NIST security level I/V (main and L5) and all main routines (KeyGen, SigGen, SigVer). Our NIST I/V designs implement the Mirath-1b-fast & Mirath-5b-fast instances, respectively, both using AES/Rijndael-based commitments.

Our paper describing the design be found on IACR ePrint.

This branch (main) contains the level I RTL code. The level V code can be found on the L5 branch.

📁 Contents

• RTL sources: verilog/vhdl (design) source files.
• TB sources: testbenches for different operations (see README for instructions).
• Other sources: constraint file for ZYNQ board.
• AES RTL sources: open-source AES core, used in our design.
• SHA-3 RTL sources: open-source SHA-3 core, used in our design.
• Patches: a collection of patches for applying to the open-source designs, according to the needs of our design

🛠️ Running Code & Testbench

Download/clone this repository using:

git clone --branch <branch-name> https://github.com/KULeuven-COSIC/MIRATH-in-HW.git

and replacing <branch-name> with main or L5

Change directory:

cd MIRATH-in-HW/

Afterwards, it is necessary to initialize the submodules:

git submodule update --init --recursive

Finally, before using the RTL in an IDE (e.g. Vivado), apply patches to the open-source code:

source patch.sh

⚙️ Getting Synthesis & Implementation results

Requirements
Our design was developed and tested with AMD Vivado, so we recommend using a machine with Vivado installed.

Vivado source setup

1. Add the contents of the src_rtl folder to Vivado as design sources.
2. Add the constraints file zynq.xdc (found in the src_util folder) using Add or create constraints.

AMD Vivado provides a wide range of synthesis and implementation directives. We used the following directives to obtain our results:

Synthesis strategy: Flow_AreaOptimized_medium (default options)

Implementation options:

1. Opt Design (enabled): Explore
2. Place Design: Auto_2
3. Post-Place Phys Opt (enabled): AggressiveExplore
4. Route Design: AggressiveExplore
5. Post-Route Phys Opt (enabled): AggressiveExplore

⚔️ Simulating the design

For detailed info on the provided simulation testbench files and how to run them, consult the related README file in the src_tb folder.

📖 Bibliography

If you use or build upon the code in this repository, please cite our paper using our CITATION key.

Licensing

See our LICENSE and further details of original sources in the accompanying NOTICE.