ErythrinaCore: A Dual-Issue Out-of-Order Machine

Contents at a glance:

• playground/src/: Chisel RTL designs.
• emulator: Simulation environment.

Command

To generate Verilog:

make verilog

To generate runnable executive file:

make verilate

To run the simulation:

make sim

To view the generated wavefile:

make wave

More details are on the way ...