differences between gddr6 model in main branch 2.0 and v2.1

[dahmadjid]

Hello

The C++ GDDR6 model on main and the Python one on v2.1 disagree a lot, and I want to know which to trust for bandwidth studies.

main (src/dram/impl/GDDR6.cpp):

• m_internal_prefetch_size = 8
• rate hardcoded to 2000 in every preset; tCK_ps = 1E6 / (m_timing_vals("rate") / 2);
• -> the modeled per-pin rate works out to ~1 Gbps (8 bits / (nBL·tCK)), far below real GDDR6

v2.1 (python/ramulator/dram/gddr6.py):

• internal_prefetch_size = 16, tCK_ps = 570 used directly
• rate = prefetch * 1e6 / (nBL * tCK) -> ~7 Gbps (double) / 14 Gbps (quad)

Questions:

1. Is the C++ rate=2000 / prefetch-8 model intentional, or superseded by v2.1?
2. Is the v2.1 rate = prefetch/(nBL*tCK) approach the intended reference?
3. Recommended way to model a realistic GDDR6 speed grade in the current C++ release?

Am I reading this correctly, or am I misunderstanding how the C++ model is meant to represent GDDR6 bandwidth?

Thanks for your efforts on the simulator, I really appreciate it. Thanks in advance for the help.

Abdelmadjid