Merge DDR3 DRAM Bender sources to master by olgunataberk · Pull Request #2 · CMU-SAFARI/DRAM-Bender

olgunataberk · 2023-05-28T10:19:51Z

Update readme
- to say that ZC706 is a supported board
- to explain how to produce a bitstream for DDR3 DRAM Bender

Copilot

Pull request overview

This PR merges the ZC706 (DDR3 DRAM Bender) hardware + host/driver sources into the repository and adds a new host-side BoardInterface option to communicate via a ZC706-specific character device driver rather than XDMA.

Changes:

Add a Linux kernel PCIe DMA + char-device driver for ZC706 (/dev/softmc_cdev) plus a simple userspace test and driver README.
Extend the host API BoardInterface to support a new IFACE::ZC706 mode alongside IFACE::XDMA.
Add the ZC706 Vivado project sources, including PCIe IP collateral, MIG/PHY sources, testbenches, and memory init .coe files.

Reviewed changes

Copilot reviewed 42 out of 130 changed files in this pull request and generated 15 comments.

Show a summary per file

File	Description
`sources/zc706_driver/test/test.c`	Adds a quick userspace read/write test for `/dev/softmc_cdev`.
`sources/zc706_driver/softmc_dma.h`	Declares driver constants, globals, and DMA buffer types for the ZC706 kernel module.
`sources/zc706_driver/softmc_dma.c`	Implements the PCIe DMA kernel module (PCI init, IRQ handler, DMA buffer ops).
`sources/zc706_driver/README.md`	Documents how to build/insert/test the ZC706 PCIe driver and switch the platform interface.
`sources/zc706_driver/Makefile`	Kernel module build rules for `dma_softmc`.
`sources/zc706_driver/cdev.h`	Declares the char-device interface used as `/dev/softmc_cdev`.
`sources/zc706_driver/cdev.c`	Implements read/write operations that bridge userspace buffers to the DMA engine.
`sources/api/board.h`	Adds `IFACE::ZC706` and declares `zc706_send/zc706_recv`.
`sources/api/board.cpp`	Implements ZC706 device open + read/write paths and routes `sendData/recvData`.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/sys_clk_gen_ps_v.txt`	Adds PCIe IP collateral file.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/synth/pcie_7x_0_ooc.xdc`	Adds PCIe IP OOC timing constraints.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0-PCIE_X0Y0.xdc`	Adds PCIe IP physical/timing constraints.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_pipe_misc.v`	Adds PCIe PIPE misc module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_brams_7x.v`	Adds PCIe BRAM wrapper module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_top_7x.v`	Adds PCIe BRAM top module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_pcie_bram_7x.v`	Adds PCIe BRAM primitive wrapper from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtx_cpllpd_ovrd.v`	Adds PCIe GT helper module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gtp_cpllpd_ovrd.v`	Adds PCIe GT helper module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_rx_valid_filter_7x.v`	Adds PCIe RX-valid filter module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_gt_common.v`	Adds PCIe GT common/QPLL wrapper wiring from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_tx.v`	Adds PCIe AXI basic TX bridge module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_top.v`	Adds PCIe AXI/TRN bridge top module from IP sources.
`projects/ZC706/ZC706.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_axi_basic_rx.v`	Adds PCIe AXI basic RX bridge module from IP sources.
`projects/ZC706/ZC706.srcs/sim_1/tb_pcie_txn_buffer.v`	Adds simulation testbench for `pcie_txn_buffer`.
`projects/ZC706/ZC706.srcs/sim_1/tb_instr_mem.v`	Adds simulation testbench for `instruction_buffer`.
`projects/ZC706/verilog/project.vh`	Adds ZC706 project-wide Verilog defines (stream width, DDR widths, etc.).
`projects/ZC706/verilog/phy/mig_7series_v4_0_poc_pd.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_poc_edge_store.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_poc_cc.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ocd_data.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_of_pre_fifo.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_ddr_if_post_fifo.v`	Adds MIG PHY module source.
`projects/ZC706/verilog/phy/mig_7series_v4_0_clk_ibuf.v`	Adds MIG clock input buffer module source.
`projects/ZC706/verilog/pcie_txn_buffer.v`	Adds a PCIe transaction buffering module (AXI-stream width conversion + buffering).
`projects/ZC706/verilog/pcie_app_7x.v`	Adds the 7-series PCIe application integration wrapper for SoftMC streams.
`projects/ZC706/verilog/instruction_buffer.v`	Adds an instruction buffering/funneling module into a wide FIFO word.
`projects/ZC706/verilog/ddr3_adapter.v`	Adds DDR3 adapter logic bridging command/control signals to the PHY interface.
`projects/ZC706/coe/pr_zq.coe`	Adds ZQ-related program memory init for ZC706.
`projects/ZC706/coe/pr_ref.coe`	Adds refresh-related program memory init for ZC706.
`projects/ZC706/coe/pr_read.coe`	Adds read-related program memory init for ZC706.

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

+    case IFACE::ZC706:
+    {
+      to_card = open("/dev/softmc_cdev", O_RDWR);
+      if (to_card < 0)
+      {
+        std::cerr << "Open to host failed!" << std::endl;
+        return 1;
+      }
+      from_card = open("/dev/softmc_cdev", O_RDWR);
+      if (from_card < 0)
+      {
+        std::cerr << "Open to card failed!" << std::endl;
+        return 1;
+      }
+    }
    default:
      std::cerr << "Unknown iface_type!" << std::endl;
      return 1;


+int BoardInterface::zc706_send(void* data, const uint size)
+{
+  uint64_t count = 0;
+  while (count < size) {
+    auto rc = write(to_card, (char*) data, size);
+    count += rc;
+  }
+  return count;
+}


+#define DEBUG
+
+#ifdef DEBUG
+#define DBG(msg) printk("%s", msg)
+#else
+#define DBG(msg) while(false)
+#endif
+
+MODULE_AUTHOR("Oguzhan Canpolat");
+MODULE_LICENSE("GPL");
+
+typedef struct {
+	char *buffer;
+	int data_count;
+	int start_off;
+	int capacity;
+} dma_buffer_t;
+
+static dma_buffer_t *send_buff;
+static dma_buffer_t *recv_buff;
+static int *txn_reg; 
+static int last_cmd;
+static int last_cmd_done;
+static struct pci_dev *dev;
+static int *device_id;
+static void __iomem *softmc_bar0;
+static wait_queue_head_t softmc_wq;
+


+	pci_read_config_word(dev, PCI_COMMAND, &val);
+	printk("pci_softmc - COMMAND: 0x%x\n", val);
+	pci_release_region(dev, 0);
+	if (pci_request_region(dev, 0, "pci_softmc_bar0")) {
+		printk("pci_softmc - could not request BAR0\n");
+		return -1;


+	uint64_t txn_reg_addr = virt_to_phys(txn_reg);
+	iowrite32((u32) (txn_reg_addr >> 32), softmc_bar0 + OFFSET_TXN_REG_LO_ADDR);
+	iowrite32((u32) (txn_reg_addr & 0xFFFFFFFF), softmc_bar0 + OFFSET_TXN_REG_HI_ADDR);


+		size_t step_size = remaining_bytes < CDEV_BUF_LEN ? remaining_bytes : CDEV_BUF_LEN; 
+		copy_from_user(cdev_buf, (buf + sent_bytes), step_size);
+		n = write_dma_buffer(cdev_buf, step_size);
+		if (n < step_size) {


+	printf("Reading once\n");
+	fread(buf, sizeof(char), BUF_LEN, fp);
+	printf("%s", buf);
+	printf("\n--------\n");
+	fread(buf, sizeof(char), BUF_LEN, fp);
+	printf("%s", buf);
+	printf("\n--------\n");


+2. Compile the ZC706 PCIe Driver with `$ make all`
+3. Insert ZC706 Driver with `$ insmod dma_softmc`
+4. Compile the driver test with `$ g++ test/*.c -o test/test`
+5. Setup ILA cores to trigger when `softmc_c2h_tvalid` or `softmc_h2c_tvalid` is asserted


+## (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##


+static void __exit exit_softmc_dma(void) {
+	printk(KERN_INFO "Unloading DMA Module.\n");
+	free_irq(dev->irq, device_id);
+	printk("pci_softmc - freed IRQ\n");
+	pci_release_region(dev, 0);
+	printk("pci_softmc - released BARs\n");
+	softmc_cdev_exit();
+	destroy_buffer(send_buff);
+	destroy_buffer(recv_buff);
+	printk(KERN_INFO "Unloaded DMA Module.\n");


kirbyydoge added 2 commits May 23, 2023 19:30

Add ZC706 Vivado Project

1369f6f

Add ZC706 PCIe Driver

38f694e

olgunataberk assigned olgunataberk and kirbyydoge May 28, 2023

kirbyydoge force-pushed the zc706 branch from 0bd3cc8 to 3f4cd4a Compare August 31, 2024 15:54

Add ZC706 to platform api and create ZC706 driver README

1554bd5

kirbyydoge force-pushed the zc706 branch from 3f4cd4a to 1554bd5 Compare August 31, 2024 15:54

kirbyydoge and others added 2 commits August 31, 2024 17:59

Update README.md

a6d879a

Change standard file functions of ZC706 driver to match XDMA driver

dfc5d64

olgunataberk requested a review from Copilot June 1, 2026 18:01

Copilot started reviewing on behalf of olgunataberk June 1, 2026 18:02 View session

Copilot AI reviewed Jun 1, 2026

View reviewed changes

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Merge DDR3 DRAM Bender sources to master#2

Merge DDR3 DRAM Bender sources to master#2
olgunataberk wants to merge 5 commits into
masterfrom
zc706

olgunataberk commented May 28, 2023

Uh oh!

Copilot AI left a comment

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

Conversation

olgunataberk commented May 28, 2023

Uh oh!

Copilot AI left a comment

Choose a reason for hiding this comment

Pull request overview

Reviewed changes

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants