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1. line line Public

   Implementation of the Brezenham algorithm on systemverilog

   SystemVerilog 1

2. WIFI-Lock WIFI-Lock Public

3. Smog-motion Smog-motion Public

4. csv2svg csv2svg Public

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5. sin_cos sin_cos Public

   generation of sin & cos on FPGA

   SystemVerilog

6. testbench3_8 testbench3_8 Public

   My testbench variant for task 3 is 8_float_discriminant synth_school

   SystemVerilog