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Add DII support for pipelining and compressed instructions
This includes removing some workarounds that modified the core in RVFI_DII mode to align with Sail with compressed instructions disabled
1 parent d47e2dc commit 75aba50

32 files changed

Lines changed: 349 additions & 373 deletions

‎.gitmodules‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,6 @@
5252
[submodule "vendor/zero-day/axi_tagcontroller"]
5353
path = vendor/zero-day/axi_tagcontroller
5454
url = https://github.com/ninolomata/axi_cheri_tagcontroller.git
55-
[submodule "corev_apu/tb/tb_testRig_cheri/src/SocketPacketUtils"]
56-
path = corev_apu/tb/tb_testRig_cheri/src/SocketPacketUtils
57-
url = https://github.com/CTSRD-CHERI/SocketPacketUtils
55+
[submodule "corev_apu/tb/tb_testRig_cheri/src/RVFI-DII-utils"]
56+
path = corev_apu/tb/tb_testRig_cheri/src/RVFI-DII-utils
57+
url = https://github.com/CTSRD-CHERI/RVFI-DII-utils.git

‎core/branch_unit.sv‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright 2018 ETH Zurich and University of Bologna.
22
// Copyright 2025 Bruno Sá and Zero-Day Labs.
3+
// Copyright 2025 Capabilities Limited.
34
// Copyright and related rights are licensed under the Solderpad Hardware
45
// License, Version 0.51 (the "License"); you may not use this file except in
56
// compliance with the License. You may obtain a copy of the License at
@@ -32,6 +33,8 @@ module branch_unit #(
3233
input fu_data_t fu_data_i,
3334
// Instruction PC - ISSUE_STAGE
3435
input logic [CVA6Cfg.PCLEN-1:0] pc_i,
36+
// Instruction stream DII ID - ISSUE_STAGE
37+
input logic [CVA6Cfg.DIIIDLEN-1:0] dii_id_i,
3538
// Instruction is compressed - ISSUE_STAGE
3639
input logic is_compressed_instr_i,
3740
// any functional unit is valid, check that there is no accidental mis-predict - TO_BE_COMPLETED
@@ -144,6 +147,7 @@ module branch_unit #(
144147
branch_result_o = next_pc;
145148
end
146149
resolved_branch_o.pc = pc_i[CVA6Cfg.VLEN-1:0];
150+
if (CVA6Cfg.RVFI_DII) resolved_branch_o.dii_id = dii_id_i;
147151
// There are only two sources of mispredicts:
148152
// 1. Branches
149153
// 2. Jumps to register addresses
@@ -198,11 +202,10 @@ module branch_unit #(
198202
target_pcc_top = target_pcc.top;
199203
target_pcc_address = target_pcc.addr;
200204
target_pcc_is_sealed = (operand_a.otype != cva6_cheri_pkg::UNSEALED_CAP);
201-
// TODO-cheri(ninolomata): fix this once we disable compressed instructions without trigering errors
202-
min_instr_off = ((CVA6Cfg.RVC && !CVA6Cfg.RVFI_DII) ? {{CVA6Cfg.XLEN-2{1'b0}}, 2'h2} : {{CVA6Cfg.XLEN-3{1'b0}}, 3'h4});
205+
min_instr_off = ((CVA6Cfg.RVC) ? {{CVA6Cfg.XLEN-2{1'b0}}, 2'h2} : {{CVA6Cfg.XLEN-3{1'b0}}, 3'h4});
203206
// Only throw instruction address misaligned exception if this is indeed a `taken` conditional branch or
204207
// an unconditional jump
205-
if (branch_valid_i && (target_address[0] || ((!CVA6Cfg.RVC || CVA6Cfg.RVFI_DII) && target_address[1])) && jump_taken) begin
208+
if (branch_valid_i && (target_address[0] || (!CVA6Cfg.RVC && target_address[1])) && jump_taken) begin
206209
branch_exception_o.valid = 1'b1;
207210
end
208211
if (CVA6Cfg.CheriPresent && branch_valid_i && jump_taken) begin

‎core/cache_subsystem/wt_cache_subsystem.sv‎

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
// Copyright 2018 ETH Zurich and University of Bologna.
2+
// Copyright 2025 Capabilities Limited.
23
// Copyright and related rights are licensed under the Solderpad Hardware
34
// License, Version 0.51 (the "License"); you may not use this file except in
45
// compliance with the License. You may obtain a copy of the License at
@@ -33,7 +34,6 @@ module wt_cache_subsystem
3334
parameter type dcache_req_o_t = logic,
3435
parameter type icache_req_t = logic,
3536
parameter type icache_rtrn_t = logic,
36-
parameter type rvfi_dii_inst_pack_t = logic,
3737
parameter int unsigned NumPorts = 4,
3838
parameter type noc_req_t = logic,
3939
parameter type noc_resp_t = logic
@@ -73,11 +73,7 @@ module wt_cache_subsystem
7373
// Invalidations
7474
input logic [63:0] inval_addr_i,
7575
input logic inval_valid_i,
76-
output logic inval_ready_o,
77-
// RVFI_DII Interface
78-
input logic rvfi_dii_rtrn_vld_i,
79-
input rvfi_dii_inst_pack_t rvfi_dii_inst_pack_i,
80-
output logic rvfi_dii_data_ready_o
76+
output logic inval_ready_o
8177
// TODO: interrupt interface
8278
);
8379

@@ -122,16 +118,12 @@ module wt_cache_subsystem
122118
.CVA6Cfg(CVA6Cfg),
123119
.icache_dreq_t(icache_dreq_t),
124120
.icache_drsp_t(icache_drsp_t),
125-
.exception_t (exception_t),
126-
.rvfi_dii_inst_pack_t (rvfi_dii_inst_pack_t)
121+
.exception_t (exception_t)
127122
) i_cva6_rvfi_dii_generator (
128123
.clk_i (clk_i),
129124
.rst_ni (rst_ni),
130125
.dreq_i (icache_dreq_i),
131-
.dreq_o (icache_dreq_o),
132-
.rvfi_dii_rtrn_vld_i (rvfi_dii_rtrn_vld_i),
133-
.rvfi_dii_inst_pack_i (rvfi_dii_inst_pack_i),
134-
.rvfi_dii_data_ready_o (rvfi_dii_data_ready_o)
126+
.dreq_o (icache_dreq_o)
135127
);
136128
assign icache_areq_o = '0;
137129
assign icache_adapter_data_req = '0;

‎core/commit_stage.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright 2018 ETH Zurich and University of Bologna.
22
// Copyright 2025 Bruno Sá and Zero-Day Labs.
3+
// Copyright 2025 Capabilities Limited.
34
// Copyright and related rights are licensed under the Solderpad Hardware
45
// License, Version 0.51 (the "License"); you may not use this file except in
56
// compliance with the License. You may obtain a copy of the License at
@@ -33,6 +34,8 @@ module commit_stage
3334
output exception_t exception_o,
3435
// Mark the F state as dirty - CSR_REGFILE
3536
output logic dirty_fp_state_o,
37+
// Last committed DII ID - FRONTEND
38+
output logic [CVA6Cfg.DIIIDLEN-1 : 0] dii_id_o,
3639
// TO_BE_COMPLETED - CSR_REGFILE
3740
input logic single_step_i,
3841
// The instruction we want to commit - ISSUE_STAGE
@@ -123,6 +126,7 @@ module commit_stage
123126
end
124127

125128
assign pc_o = commit_instr_i[0].pc;
129+
if (CVA6Cfg.RVFI_DII) assign dii_id_o = commit_instr_i[0].dii_id;
126130
// Dirty the FP state if we are committing anything related to the FPU
127131
always_comb begin : dirty_fp_state
128132
dirty_fp_state_o = 1'b0;

‎core/csr_regfile.sv‎

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright 2018 ETH Zurich and University of Bologna.
22
// Copyright 2025 Bruno Sá and Zero-Day Labs.
3+
// Copyright 2025 Capabilities Limited.
34
// Copyright and related rights are licensed under the Solderpad Hardware
45
// License, Version 0.51 (the "License"); you may not use this file except in
56
// compliance with the License. You may obtain a copy of the License at
@@ -397,9 +398,6 @@ if (CVA6Cfg.CheriPresent) begin
397398
riscv::CSR_MEPC: begin
398399
wr_cap = mepcc_q;
399400
wr_cap_addr = {csr_wdata[riscv::XLEN-1:1], 1'b0};
400-
// TODO-ninolomata(cheri): fix this
401-
if (CVA6Cfg.RVFI_DII)
402-
wr_cap_addr = {csr_wdata[riscv::XLEN-1:2], 2'b0};
403401
end
404402
riscv::CSR_MTVEC: begin
405403
wr_cap = mtcc_q;
@@ -417,9 +415,6 @@ if (CVA6Cfg.CheriPresent) begin
417415
riscv::CSR_SEPC: begin
418416
wr_cap = sepcc_q;
419417
wr_cap_addr = {csr_wdata[riscv::XLEN-1:1], 1'b0};
420-
// TODO-ninolomata(cheri): fix this
421-
if (CVA6Cfg.RVFI_DII)
422-
wr_cap_addr = {csr_wdata[riscv::XLEN-1:2], 2'b0};
423418
end
424419
riscv::CSR_STVEC: begin
425420
wr_cap = stcc_q;
@@ -1218,7 +1213,6 @@ end
12181213
sscratchc_d = scr_wdata;
12191214
end
12201215
cva6_cheri_pkg::SCR_SEPCC: begin
1221-
// TODO-cheri(ninolomata):fix this it should clear bit 1 only
12221216
sepcc_d = cva6_cheri_pkg::set_cap_reg_addr(scr_wdata, {scr_wdata[CVA6Cfg.XLEN-1:1], 1'b0});
12231217
end
12241218
cva6_cheri_pkg::SCR_MTCC: begin
@@ -1237,8 +1231,6 @@ end
12371231
mscratchc_d = scr_wdata;
12381232
end
12391233
cva6_cheri_pkg::SCR_MEPCC: begin
1240-
// TODO-cheri(ninolomata):fix this it should clear bit 1 only
1241-
//mepcc_d = cva6_cheri_pkg::set_cap_reg_addr(scr_wdata, {scr_wdata[CVA6Cfg.XLEN-1:2], 2'b00});
12421234
mepcc_d = cva6_cheri_pkg::set_cap_reg_addr(scr_wdata, {scr_wdata[CVA6Cfg.XLEN-1:1], 1'b0});
12431235
end
12441236
default: begin

‎core/cva6.sv‎

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright 2017-2019 ETH Zurich and University of Bologna.
22
// Copyright 2025 Bruno Sá and Zero-Day Labs.
3+
// Copyright 2025 Capabilities Limited.
34
// Copyright and related rights are licensed under the Solderpad Hardware
45
// License, Version 0.51 (the "License"); you may not use this file except in
56
// compliance with the License. You may obtain a copy of the License at
@@ -30,7 +31,6 @@ module cva6
3031
logic csr;
3132
rvfi_probes_instr_t instr;
3233
},
33-
parameter type rvfi_dii_inst_pack_t = `RVFI_DII_INSTR_T(CVA6Cfg),
3434

3535
// branchpredict scoreboard entry
3636
// this is the struct which we will inject into the pipeline to guide the various
@@ -66,6 +66,7 @@ module cva6
6666
// I$ data requests
6767
localparam type icache_dreq_t = struct packed {
6868
logic req; // we request a new word
69+
logic [CVA6Cfg.DIIIDLEN-1:0] dii_id; // next requested DII ID in instruction stream
6970
logic kill_s1; // kill the current request
7071
logic kill_s2; // kill the last request
7172
logic spec; // request is speculative
@@ -78,13 +79,15 @@ module cva6
7879
logic [CVA6Cfg.FETCH_WIDTH-1:0] data; // 2+ cycle out: tag
7980
logic [CVA6Cfg.FETCH_USER_WIDTH-1:0] user; // User bits
8081
logic [CVA6Cfg.VLEN-1:0] vaddr; // virtual address out
82+
logic [CVA6Cfg.DIIIDLEN-1:0] dii_id; // First DII ID in the returned data
8183
exception_t ex; // we've encountered an exception
8284
},
8385

8486
// IF/ID Stage
8587
// store the decompressed instruction
8688
localparam type fetch_entry_t = struct packed {
8789
logic [CVA6Cfg.PCLEN-1:0] address; // the address of the instructions from below
90+
logic [CVA6Cfg.DIIIDLEN-1:0] dii_id; // the DII ID of the instruction in the stream
8891
logic [31:0] instruction; // instruction word
8992
branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path
9093
exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions
@@ -93,6 +96,7 @@ module cva6
9396
// ID/EX/WB Stage
9497
localparam type scoreboard_entry_t = struct packed {
9598
logic [CVA6Cfg.PCLEN-1:0] pc; // PC of instruction
99+
logic [CVA6Cfg.DIIIDLEN-1:0] dii_id; // DII ID of the instruction in the stream
96100
logic [CVA6Cfg.REGLEN-1:0] ddc;
97101
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry
98102
// with the transaction id in any case make the width more generic
@@ -130,6 +134,7 @@ module cva6
130134
localparam type bp_resolve_t = struct packed {
131135
logic valid; // prediction with all its values is valid
132136
logic [CVA6Cfg.VLEN-1:0] pc; // PC of predict or mis-predict
137+
logic [CVA6Cfg.DIIIDLEN-1:0] dii_id; // dii id of branch
133138
logic [CVA6Cfg.PCLEN-1:0] target_address; // target address at which to jump, or not
134139
logic is_mispredict; // set if this was a mis-predict
135140
logic is_taken; // branch is taken
@@ -311,9 +316,6 @@ module cva6
311316
input logic debug_req_i,
312317
// Probes to build RVFI, can be left open when not used - RVFI
313318
output rvfi_probes_t rvfi_probes_o,
314-
input logic rvfi_dii_rtrn_vld_i,
315-
input rvfi_dii_inst_pack_t rvfi_dii_inst_pack_i,
316-
output logic rvfi_dii_data_ready_o,
317319
// CVXIF request - SUBSYSTEM
318320
output cvxif_req_t cvxif_req_o,
319321
// CVXIF response - SUBSYSTEM
@@ -359,6 +361,7 @@ module cva6
359361
exception_t ex_commit; // exception from commit stage
360362
bp_resolve_t resolved_branch;
361363
logic [ CVA6Cfg.PCLEN-1:0] pc_commit;
364+
logic [ CVA6Cfg.DIIIDLEN-1:0] dii_id_commit;
362365
logic eret;
363366
logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack;
364367
logic [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack;
@@ -396,6 +399,7 @@ module cva6
396399

397400
fu_data_t fu_data_id_ex;
398401
logic [CVA6Cfg.PCLEN-1:0] pc_id_ex;
402+
logic [CVA6Cfg.DIIIDLEN-1:0] dii_id_id_ex;
399403
logic is_compressed_instr_id_ex;
400404
logic [31:0] tinst_ex;
401405
// fixed latency units
@@ -564,6 +568,7 @@ module cva6
564568
logic flush_csr_ctrl;
565569
logic flush_unissued_instr_ctrl_id;
566570
logic flush_ctrl_if;
571+
logic [CVA6Cfg.DIIIDLEN-1:0] flush_ctrl_dii_id_if;
567572
logic flush_ctrl_id;
568573
logic flush_ctrl_ex;
569574
logic flush_ctrl_bp;
@@ -634,6 +639,7 @@ module cva6
634639
.icache_dreq_o (icache_dreq_if_cache),
635640
.resolved_branch_i (resolved_branch),
636641
.pc_commit_i (pc_commit),
642+
.dii_id_commit_i (dii_id_commit),
637643
.set_pc_commit_i (set_pc_ctrl_pcgen),
638644
.set_debug_pc_i (set_debug_pc),
639645
.epc_i (epc_commit_pcgen),
@@ -785,6 +791,7 @@ module cva6
785791
.rs2_forwarding_o (rs2_forwarding_id_ex),
786792
.fu_data_o (fu_data_id_ex),
787793
.pc_o (pc_id_ex),
794+
.dii_id_o (dii_id_id_ex),
788795
.is_compressed_instr_o (is_compressed_instr_id_ex),
789796
.tinst_o (tinst_ex),
790797
// fixed latency unit ready
@@ -866,6 +873,7 @@ module cva6
866873
.rs2_forwarding_i(rs2_forwarding_id_ex),
867874
.fu_data_i(fu_data_id_ex),
868875
.pc_i(pc_id_ex),
876+
.dii_id_i(dii_id_id_ex),
869877
.is_compressed_instr_i(is_compressed_instr_id_ex),
870878
.tinst_i(tinst_ex),
871879
// fixed latency units
@@ -1015,6 +1023,7 @@ module cva6
10151023
.amo_resp_i (amo_resp),
10161024
.commit_csr_o (csr_commit_commit_ex),
10171025
.pc_o (pc_commit),
1026+
.dii_id_o (dii_id_commit),
10181027
.csr_op_o (csr_op_commit_csr),
10191028
.csr_wdata_o (csr_wdata_commit_csr),
10201029
.csr_rdata_i (csr_rdata_csr_commit),
@@ -1248,7 +1257,6 @@ module cva6
12481257
.dcache_req_i_t(dcache_req_i_t),
12491258
.dcache_req_o_t(dcache_req_o_t),
12501259
.exception_t (exception_t),
1251-
.rvfi_dii_inst_pack_t(rvfi_dii_inst_pack_t),
12521260
.NumPorts (NumPorts),
12531261
.noc_req_t (noc_req_t),
12541262
.noc_resp_t(noc_resp_t)
@@ -1284,10 +1292,7 @@ module cva6
12841292
.noc_resp_i (noc_resp_i),
12851293
.inval_addr_i (inval_addr),
12861294
.inval_valid_i (inval_valid),
1287-
.inval_ready_o (inval_ready),
1288-
.rvfi_dii_rtrn_vld_i (rvfi_dii_rtrn_vld_i),
1289-
.rvfi_dii_inst_pack_i (rvfi_dii_inst_pack_i),
1290-
.rvfi_dii_data_ready_o (rvfi_dii_data_ready_o)
1295+
.inval_ready_o (inval_ready)
12911296
);
12921297
end else if (CVA6Cfg.DCacheType == config_pkg::HPDCACHE) begin : gen_cache_hpd
12931298
cva6_hpdcache_subsystem #(

‎core/cva6_rvfi.sv‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright 2024 Thales DIS France SAS
22
// Copyright 2025 Bruno Sá and Zero-Day Labs.
3+
// Copyright 2025 Capabilities Limited.
34
//
45
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
56
// you may not use this file except in compliance with the License.
@@ -270,9 +271,11 @@ module cva6_rvfi
270271

271272
always_ff @(posedge clk_i) begin
272273
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
274+
logic [31:0] instr;
273275
logic exception;
274276
logic [4:0] rd_addr;
275277
logic [4:0] rs2_addr;
278+
instr = mem_q[commit_pointer[i]].instr;
276279
exception = commit_instr_valid[i][0] && ex_commit_valid;
277280
rd_addr = commit_instr_rd[i][4:0];
278281
rs2_addr = (is_amo_sc(commit_instr_op[i]) && wdata[i] == 1) ? '0 : commit_instr_rs2[i][4:0];
@@ -281,7 +284,7 @@ module cva6_rvfi
281284
ex_commit_cause == riscv::ENV_CALL_SMODE ||
282285
ex_commit_cause == riscv::ENV_CALL_UMODE ||
283286
ex_commit_cause == cva6_cheri_pkg::CAP_EXCEPTION));
284-
rvfi_instr_o[i].insn <= mem_q[commit_pointer[i]].instr;
287+
rvfi_instr_o[i].insn <= instr;
285288
// when trap, the instruction is not executed
286289
rvfi_instr_o[i].trap <= exception;
287290
rvfi_instr_o[i].cause <= ex_commit_cause;
@@ -294,12 +297,12 @@ module cva6_rvfi
294297
commit_instr_op[i]
295298
)) ? commit_instr_result[i] : wdata[i];
296299
rvfi_instr_o[i].pc_rdata <= commit_instr_pc[i];
297-
if (mem_q[commit_pointer[i]].instr == 32'h30200073 && !exception) begin
300+
if (instr == 32'h30200073 && !exception) begin
298301
rvfi_instr_o[i].pc_wdata <= csr.mepcc_q[63:0];
299-
end else if (mem_q[commit_pointer[i]].instr == 32'h10200073 && !exception) begin
302+
end else if (instr == 32'h10200073 && !exception) begin
300303
rvfi_instr_o[i].pc_wdata <= csr.sepcc_q[63:0];
301304
end else begin
302-
rvfi_instr_o[i].pc_wdata <= (exception) ? {csr.mtcc_q[63:2], 2'b00} : (commit_instr_fu[i] == CTRL_FLOW) ? commit_instr_next_pc[i] : commit_instr_pc[i] + 4;
305+
rvfi_instr_o[i].pc_wdata <= (exception) ? {csr.mtcc_q[63:2], 2'b00} : (commit_instr_fu[i] == CTRL_FLOW) ? commit_instr_next_pc[i] : commit_instr_pc[i] + (instr[1:0] == 2'b11 ? 4 : 2);
303306
end
304307
rvfi_instr_o[i].mem_addr <= mem_q[commit_pointer[i]].lsu_addr + ((commit_instr_op[i] == ariane_pkg::CLOAD_TAGS) ? 0 : 0);
305308
// So far, only write paddr is reported. TODO: read paddr

‎core/decoder.sv‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
// Copyright 2018 ETH Zurich and University of Bologna.
22
// Copyright 2025 Bruno Sá and Zero-Day Labs.
3+
// Copyright 2025 Capabilities Limited.
34
// Copyright and related rights are licensed under the Solderpad Hardware
45
// License, Version 0.51 (the "License"); you may not use this file except in
56
// compliance with the License. You may obtain a copy of the License at
@@ -36,6 +37,7 @@ module decoder
3637
// PC from fetch stage - FRONTEND
3738
// TODO-cheri: make cheri optional
3839
input logic [CVA6Cfg.PCLEN-1:0] pc_i,
40+
input logic [CVA6Cfg.DIIIDLEN-1:0] dii_id_i,
3941
// Is a compressed instruction - compressed_decoder
4042
input logic is_compressed_i,
4143
// Compressed form of instruction - FRONTEND
@@ -191,6 +193,7 @@ module decoder
191193
instruction_o.use_zimm = 1'b0;
192194
instruction_o.bp = branch_predict_i;
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instruction_o.vfp = 1'b0;
196+
if (CVA6Cfg.RVFI_DII) instruction_o.dii_id = dii_id_i;
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if (CVA6Cfg.CheriPresent) begin
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instruction_o.ddc = ddc_i;
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instruction_o.use_ddc = 1'b0;

‎core/ex_stage.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11

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// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright 2025 Bruno Sá and Zero-Day Labs.
4+
// Copyright 2025 Capabilities Limited.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
@@ -47,6 +48,8 @@ module ex_stage
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input fu_data_t fu_data_i,
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// PC of the current instruction - ISSUE_STAGE
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input logic [CVA6Cfg.PCLEN-1:0] pc_i,
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// DII ID of the current instruction - ISSUE_STAGE
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input logic [CVA6Cfg.DIIIDLEN-1:0] dii_id_i,
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// DDC of the current instruction - ISSUE_STAGE
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input logic [CVA6Cfg.REGLEN-1:0] ddc_i,
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// Report whether isntruction is compressed - ISSUE_STAGE
@@ -306,6 +309,7 @@ module ex_stage
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.debug_mode_i,
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.fu_data_i,
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.pc_i,
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.dii_id_i,
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.is_compressed_instr_i,
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// any functional unit is valid, check that there is no accidental mis-predict
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.fu_valid_i ( alu_valid_i || lsu_valid_i || csr_valid_i || mult_valid_i || fpu_valid_i || acc_valid_i ) ,

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