The bigger STM chips have giant pages of 128kb.
This makes sequential-storage pretty slow, pretty much mandating cache.
A solution to this would be virtual pages. We could split up the big page in smaller logical pages. This will aid in seek speed.
Of course you can't erase a virtual page without erasing the rest, so that would require some more administration and checking of assumptions.
It may require an extra page state though, so that might make things difficult.
I'm thinking that because we'd need to mark a page as being virtually open/erased somehow.
The bigger STM chips have giant pages of 128kb.
This makes sequential-storage pretty slow, pretty much mandating cache.
A solution to this would be virtual pages. We could split up the big page in smaller logical pages. This will aid in seek speed.
Of course you can't erase a virtual page without erasing the rest, so that would require some more administration and checking of assumptions.
It may require an extra page state though, so that might make things difficult.
I'm thinking that because we'd need to mark a page as being virtually open/erased somehow.