@@ -1894,6 +1894,8 @@ def test_option_show_config(self):
18941894 "Screen=0\n "
18951895 "ScreenFps=50\n "
18961896 "ScreenScale=2\n "
1897+ "TraceHeader=\n "
1898+ "TraceHeader2=\n "
18971899 "TraceLine=${pc:04X} {i}\n "
18981900 "TraceLine2=${pc:04X} {i:<15} "
18991901 "A={r[a]:02X} F={r[f]:08b} BC={r[bc]:04X} DE={r[de]:04X} HL={r[hl]:04X} IX={r[ix]:04X} IY={r[iy]:04X}\\ n "
@@ -1922,6 +1924,8 @@ def test_option_show_config_read_from_file(self):
19221924 Screen=0
19231925 ScreenFps=50
19241926 ScreenScale=2
1927+ TraceHeader=
1928+ TraceHeader2=
19251929 TraceLine=${pc:04X} {i}
19261930 TraceLine2=${pc:04x} {i:<15} A={r[a]:02X}
19271931 TraceLineDecimal={pc:05} {i}
@@ -2479,6 +2483,121 @@ def test_config_ScreenScale_set_on_command_line(self):
24792483 self .assertEqual (screen .scr [0 ], 16 )
24802484 self .assertEqual (screen .frame , 1 )
24812485
2486+ def test_config_TraceHeader_read_from_file (self ):
2487+ ini = """
2488+ [trace]
2489+ TraceHeader=ADDR DISASSEMBLY
2490+ """
2491+ self .write_text_file (dedent (ini ).strip (), 'skoolkit.ini' )
2492+ code = (
2493+ 0x06 , 0x02 , # $8000 LD B,$02
2494+ 0x0E , 0x03 , # $8002 LD C,$03
2495+ )
2496+ binfile = self .write_bin_file (code , suffix = '.bin' )
2497+ start = 0x8000
2498+ stop = start + len (code )
2499+ output , error = self .run_trace (f'-n -o { start } -S { stop } -v { binfile } ' )
2500+ self .assertEqual (error , '' )
2501+ exp_output = """
2502+ ADDR DISASSEMBLY
2503+ $8000 LD B,$02
2504+ $8002 LD C,$03
2505+ Stopped at $8004
2506+ """
2507+ self .assertEqual (dedent (exp_output ).strip (), output .rstrip ())
2508+
2509+ def test_config_TraceHeader_set_on_command_line (self ):
2510+ code = (
2511+ 0x06 , 0x02 , # $8000 LD B,$02
2512+ 0x0E , 0x03 , # $8002 LD C,$03
2513+ )
2514+ binfile = self .write_bin_file (code , suffix = '.bin' )
2515+ start = 0x8000
2516+ stop = start + len (code )
2517+ header = 'Addr Disassembly'
2518+ output , error = self .run_trace (('-n' , '-I' , f'TraceHeader={ header } ' , '-o' , str (start ), '-S' , str (stop ), '-v' , binfile ))
2519+ self .assertEqual (error , '' )
2520+ exp_output = """
2521+ Addr Disassembly
2522+ $8000 LD B,$02
2523+ $8002 LD C,$03
2524+ Stopped at $8004
2525+ """
2526+ self .assertEqual (dedent (exp_output ).strip (), output .rstrip ())
2527+
2528+ def test_config_TraceHeader_with_newline (self ):
2529+ code = (
2530+ 0x06 , 0x02 , # $8000 LD B,$02
2531+ 0x0E , 0x03 , # $8002 LD C,$03
2532+ )
2533+ binfile = self .write_bin_file (code , suffix = '.bin' )
2534+ start = 0x8000
2535+ stop = start + len (code )
2536+ header = r'Addr Disassembly\n==== ==========='
2537+ output , error = self .run_trace (('-n' , '-I' , f'TraceHeader={ header } ' , '-o' , str (start ), '-S' , str (stop ), '-v' , binfile ))
2538+ self .assertEqual (error , '' )
2539+ exp_output = """
2540+ Addr Disassembly
2541+ ==== ===========
2542+ $8000 LD B,$02
2543+ $8002 LD C,$03
2544+ Stopped at $8004
2545+ """
2546+ self .assertEqual (dedent (exp_output ).strip (), output .rstrip ())
2547+
2548+ def test_config_TraceHeader2_read_from_file (self ):
2549+ ini = """
2550+ [trace]
2551+ TraceHeader2=ADDR DISASSEMBLY REGISTERS
2552+ """
2553+ self .write_text_file (dedent (ini ).strip (), 'skoolkit.ini' )
2554+ code = (0x3E , 0x01 ) # $8000 LD A,$01
2555+ binfile = self .write_bin_file (code , suffix = '.bin' )
2556+ start = 0x8000
2557+ stop = start + len (code )
2558+ output , error = self .run_trace (f'-n -o { start } -S { stop } -vv { binfile } ' )
2559+ self .assertEqual (error , '' )
2560+ exp_output = """
2561+ ADDR DISASSEMBLY REGISTERS
2562+ $8000 LD A,$01 A=01 F=00000000 BC=0000 DE=0000 HL=0000 IX=0000 IY=5C3A
2563+ A'=00 F'=00000000 BC'=0000 DE'=0000 HL'=0000 SP=5C00 IR=3F01
2564+ Stopped at $8002
2565+ """
2566+ self .assertEqual (dedent (exp_output ).strip (), output .rstrip ())
2567+
2568+ def test_config_TraceHeader2_set_on_command_line (self ):
2569+ code = (0x3E , 0x01 ) # $8000 LD A,$01
2570+ binfile = self .write_bin_file (code , suffix = '.bin' )
2571+ start = 0x8000
2572+ stop = start + len (code )
2573+ header = 'Addr Disassembly Registers'
2574+ output , error = self .run_trace (('-n' , '-I' , f'TraceHeader2={ header } ' , '-o' , str (start ), '-S' , str (stop ), '-vv' , binfile ))
2575+ self .assertEqual (error , '' )
2576+ exp_output = """
2577+ Addr Disassembly Registers
2578+ $8000 LD A,$01 A=01 F=00000000 BC=0000 DE=0000 HL=0000 IX=0000 IY=5C3A
2579+ A'=00 F'=00000000 BC'=0000 DE'=0000 HL'=0000 SP=5C00 IR=3F01
2580+ Stopped at $8002
2581+ """
2582+ self .assertEqual (dedent (exp_output ).strip (), output .rstrip ())
2583+
2584+ def test_config_TraceHeader2_with_newline (self ):
2585+ code = (0x3E , 0x01 ) # $8000 LD A,$01
2586+ binfile = self .write_bin_file (code , suffix = '.bin' )
2587+ start = 0x8000
2588+ stop = start + len (code )
2589+ header = r'Addr Disassembly Registers\n==== =========== ========='
2590+ output , error = self .run_trace (('-n' , '-I' , f'TraceHeader2={ header } ' , '-o' , str (start ), '-S' , str (stop ), '-vv' , binfile ))
2591+ self .assertEqual (error , '' )
2592+ exp_output = """
2593+ Addr Disassembly Registers
2594+ ==== =========== =========
2595+ $8000 LD A,$01 A=01 F=00000000 BC=0000 DE=0000 HL=0000 IX=0000 IY=5C3A
2596+ A'=00 F'=00000000 BC'=0000 DE'=0000 HL'=0000 SP=5C00 IR=3F01
2597+ Stopped at $8002
2598+ """
2599+ self .assertEqual (dedent (exp_output ).strip (), output .rstrip ())
2600+
24822601 def test_config_TraceLine_read_from_file (self ):
24832602 ini = """
24842603 [trace]
0 commit comments