sim_top

#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "D:\iverilog\lib\ivl\system.vpi";
:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
:vpi_module "D:\iverilog\lib\ivl\v2009.vpi";
S_00000143743232c0 .scope package, "$unit" "$unit" 2 1;
 .timescale 0 0;
S_00000143743227d0 .scope module, "tb_top_receiver" "tb_top_receiver" 3 3;
 .timescale -9 -12;
P_00000143742add30 .param/l "CLK_PERIOD" 0 3 7, +C4<00000000000000000000000000001010>;
P_00000143742add68 .param/l "DATA_W" 0 3 6, +C4<00000000000000000000000000010000>;
P_00000143742adda0 .param/l "MEM_ADC_LEN" 1 3 40, +C4<000000000000000000000000001010000>;
P_00000143742addd8 .param/l "NCP" 0 3 9, +C4<00000000000000000000000000010000>;
P_00000143742ade10 .param/l "NFFT" 0 3 8, +C4<00000000000000000000000001000000>;
v00000143743a3060_0 .var/i "abs_err_x1_im", 31 0;
v00000143743a45a0_0 .var/i "abs_err_x1_re", 31 0;
v00000143743a39c0_0 .var/i "abs_err_x2_im", 31 0;
v00000143743a3b00_0 .var/i "abs_err_x2_re", 31 0;
v00000143743a4dc0_0 .var/s "adc1_im", 15 0;
v00000143743a4500_0 .var/s "adc1_re", 15 0;
v00000143743a3380_0 .var/s "adc2_im", 15 0;
v00000143743a3600_0 .var/s "adc2_re", 15 0;
v00000143743a36a0_0 .var/i "adc_feed_idx", 31 0;
v00000143743a3ba0_0 .var "clk", 0 0;
v00000143743a43c0_0 .net/s "cpe_phase_err_dbg", 15 0, L_00000143743047a0;  1 drivers
v00000143743a3560_0 .net "cpe_phase_valid_dbg", 0 0, L_0000014374303930;  1 drivers
v00000143743a3240_0 .var "expected_bits", 3 0;
v00000143743a4d20_0 .var/s "g_x1_im", 15 0;
v00000143743a4c80_0 .var/s "g_x1_re", 15 0;
v00000143743a50e0_0 .var/s "g_x2_im", 15 0;
v00000143743a32e0_0 .var/s "g_x2_re", 15 0;
v00000143743a4640_0 .var/s "gz_x1_im", 15 0;
v00000143743a3740_0 .var/s "gz_x1_re", 15 0;
v00000143743a4280_0 .var/s "gz_x2_im", 15 0;
v00000143743a4460_0 .var/s "gz_x2_re", 15 0;
v00000143743a37e0_0 .var/s "h00_im", 15 0;
v00000143743a46e0_0 .var/s "h00_re", 15 0;
v00000143743a4960_0 .var/s "h01_im", 15 0;
v00000143743a2980_0 .var/s "h01_re", 15 0;
v00000143743a4fa0_0 .var/s "h10_im", 15 0;
v00000143743a3100_0 .var/s "h10_re", 15 0;
v00000143743a3c40_0 .var/s "h11_im", 15 0;
v00000143743a3880_0 .var/s "h11_re", 15 0;
v00000143743a2e80_0 .var/i "i", 31 0;
v00000143743a4780_0 .var "in_valid", 0 0;
v00000143743a4aa0_0 .var/i "matched_cnt", 31 0;
v00000143743a3420_0 .var/i "max_err_x1_im", 31 0;
v00000143743a4be0_0 .var/i "max_err_x1_re", 31 0;
v00000143743a2de0_0 .var/i "max_err_x2_im", 31 0;
v00000143743a3920_0 .var/i "max_err_x2_re", 31 0;
v00000143743a3a60 .array "mem_adc_time", 79 0, 63 0;
v00000143743a3d80 .array "mem_final_out", 63 0, 63 0;
v00000143743a3e20 .array "mem_h_inv", 3 0, 31 0;
v00000143743a4e60 .array "mem_zf_out", 63 0, 63 0;
v00000143743a4f00_0 .var/i "mismatch_cnt", 31 0;
v00000143743a3ec0_0 .net/s "nco_acc_dbg", 15 0, L_0000014374303fc0;  1 drivers
v00000143743a2b60_0 .var/i "out_idx", 31 0;
v00000143743a3f60_0 .net "out_valid", 0 0, v0000014374388060_0;  1 drivers
v00000143743a4820_0 .var "rst_n", 0 0;
v00000143743a2ca0_0 .net "rx_bits", 3 0, v00000143743878e0_0;  1 drivers
v00000143743a4a00_0 .var/i "zf_idx", 31 0;
v00000143743a48c0_0 .var/i "zf_matched_cnt", 31 0;
v00000143743a5040_0 .var/i "zf_mismatch_cnt", 31 0;
v00000143743a40a0_0 .net "zf_valid_dbg", 0 0, L_00000143743031c0;  1 drivers
v00000143743a4320_0 .net/s "zf_x1_im_dbg", 15 0, L_0000014374304ab0;  1 drivers
v00000143743a4140_0 .net/s "zf_x1_re_dbg", 15 0, L_0000014374303ee0;  1 drivers
v00000143743a41e0_0 .net/s "zf_x2_im_dbg", 15 0, L_0000014374304110;  1 drivers
v00000143743a2c00_0 .net/s "zf_x2_re_dbg", 15 0, L_0000014374304b90;  1 drivers
E_00000143742d2010 .event anyedge, v00000143743a2b60_0;
E_00000143742d1b10 .event anyedge, v0000014374381260_0;
S_0000014374323450 .scope function.vec4.u32, "abs16" "abs16" 3 179, 3 179 0, S_00000143743227d0;
 .timescale -9 -12;
; Variable abs16 is vec4 return value of scope S_0000014374323450
v00000143742e4d70_0 .var/s "v", 15 0;
TD_tb_top_receiver.abs16 ;
    %load/vec4 v00000143742e4d70_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_mov 8, 5;
    %jmp/0 T_0.0, 8;
    %load/vec4 v00000143742e4d70_0;
    %pad/s 32;
    %inv;
    %pushi/vec4 1, 0, 32;
    %add;
    %jmp/1 T_0.1, 8;
T_0.0 ; End of true expr.
    %load/vec4 v00000143742e4d70_0;
    %pad/s 32;
    %jmp/0 T_0.1, 8;
 ; End of false expr.
    %blend;
T_0.1;
    %ret/vec4 0, 0, 32;  Assign to abs16 (store_vec4_to_lval)
    %end;
S_0000014374323130 .scope module, "u_top" "mimo_ofdm_rx_top" 3 52, 4 1 0, S_00000143743227d0;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "in_valid";
    .port_info 3 /INPUT 16 "adc1_re";
    .port_info 4 /INPUT 16 "adc1_im";
    .port_info 5 /INPUT 16 "adc2_re";
    .port_info 6 /INPUT 16 "adc2_im";
    .port_info 7 /INPUT 16 "h00_re";
    .port_info 8 /INPUT 16 "h00_im";
    .port_info 9 /INPUT 16 "h01_re";
    .port_info 10 /INPUT 16 "h01_im";
    .port_info 11 /INPUT 16 "h10_re";
    .port_info 12 /INPUT 16 "h10_im";
    .port_info 13 /INPUT 16 "h11_re";
    .port_info 14 /INPUT 16 "h11_im";
    .port_info 15 /OUTPUT 1 "out_valid";
    .port_info 16 /OUTPUT 4 "rx_bits";
    .port_info 17 /OUTPUT 1 "zf_valid_tap";
    .port_info 18 /OUTPUT 1 "cpe_phase_valid_tap";
    .port_info 19 /OUTPUT 16 "zf_x1_re_tap";
    .port_info 20 /OUTPUT 16 "zf_x1_im_tap";
    .port_info 21 /OUTPUT 16 "zf_x2_re_tap";
    .port_info 22 /OUTPUT 16 "zf_x2_im_tap";
    .port_info 23 /OUTPUT 16 "cpe_phase_err_tap";
    .port_info 24 /OUTPUT 16 "nco_acc_tap";
P_00000143742f7a30 .param/l "DATA_W" 0 4 2, +C4<00000000000000000000000000010000>;
P_00000143742f7a68 .param/l "DEBUG_BYPASS_ROT" 0 4 3, +C4<00000000000000000000000000000000>;
P_00000143742f7aa0 .param/l "S_READ" 1 4 284, +C4<00000000000000000000000000000001>;
P_00000143742f7ad8 .param/l "S_WAIT" 1 4 284, +C4<00000000000000000000000000000000>;
L_0000014374304570 .functor BUFZ 16, v000001437438bb70_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374303690 .functor AND 1, v0000014374390970_0, L_0000014374408060, C4<1>, C4<1>;
L_0000014374303070 .functor AND 1, L_0000014374303690, L_00000143744073e0, C4<1>, C4<1>;
L_00000143743031c0 .functor BUFZ 1, v000001437439db70_0, C4<0>, C4<0>, C4<0>;
L_0000014374303ee0 .functor BUFZ 16, v000001437439d210_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374304ab0 .functor BUFZ 16, v000001437439f5b0_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374304b90 .functor BUFZ 16, v000001437439ee30_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374304110 .functor BUFZ 16, v000001437439d2b0_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374303930 .functor BUFZ 1, v0000014374384740_0, C4<0>, C4<0>, C4<0>;
L_00000143743047a0 .functor BUFZ 16, v00000143743856e0_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
v000001437439d7b0_0 .net/s "X1_im", 15 0, v000001437439f5b0_0;  1 drivers
v000001437439d490_0 .net/s "X1_re", 15 0, v000001437439d210_0;  1 drivers
v000001437439d530_0 .net/s "X1c_im", 15 0, v0000014374385aa0_0;  1 drivers
v000001437439d670_0 .net/s "X1c_re", 15 0, v0000014374385b40_0;  1 drivers
v000001437439d5d0_0 .net/s "X2_im", 15 0, v000001437439d2b0_0;  1 drivers
v000001437439d850_0 .net/s "X2_re", 15 0, v000001437439ee30_0;  1 drivers
v000001437439d990_0 .net/s "X2c_im", 15 0, v0000014374385c80_0;  1 drivers
v000001437439e890_0 .net/s "X2c_re", 15 0, v0000014374385fa0_0;  1 drivers
v000001437439e570_0 .net *"_ivl_11", 0 0, L_0000014374303690;  1 drivers
v000001437439e390_0 .net *"_ivl_12", 31 0, L_0000014374407e80;  1 drivers
L_00000143743a9458 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v000001437439e070_0 .net *"_ivl_15", 24 0, L_00000143743a9458;  1 drivers
L_00000143743a94a0 .functor BUFT 1, C4<00000000000000000000000001010000>, C4<0>, C4<0>, C4<0>;
v000001437439e1b0_0 .net/2u *"_ivl_16", 31 0, L_00000143743a94a0;  1 drivers
v000001437439e250_0 .net *"_ivl_18", 0 0, L_00000143744073e0;  1 drivers
v000001437439eb10_0 .net *"_ivl_2", 31 0, L_00000143744087e0;  1 drivers
L_00000143743a93c8 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v000001437439e2f0_0 .net *"_ivl_5", 24 0, L_00000143743a93c8;  1 drivers
L_00000143743a9410 .functor BUFT 1, C4<00000000000000000000000000001111>, C4<0>, C4<0>, C4<0>;
v000001437439e430_0 .net/2u *"_ivl_6", 31 0, L_00000143743a9410;  1 drivers
v000001437439e4d0_0 .net *"_ivl_8", 0 0, L_0000014374408060;  1 drivers
v000001437439e610_0 .net/s "adc1_im", 15 0, v00000143743a4dc0_0;  1 drivers
v000001437439e6b0_0 .net/s "adc1_re", 15 0, v00000143743a4500_0;  1 drivers
v000001437439e750_0 .net/s "adc2_im", 15 0, v00000143743a3380_0;  1 drivers
v000001437439e7f0_0 .net/s "adc2_re", 15 0, v00000143743a3600_0;  1 drivers
v000001437439e930 .array/s "buf1_im", 79 0, 15 0;
v000001437439e9d0 .array/s "buf1_re", 79 0, 15 0;
v000001437439ea70 .array/s "buf2_im", 79 0, 15 0;
v000001437439ec50 .array/s "buf2_re", 79 0, 15 0;
v00000143743a0050_0 .var "buf_rd_idx", 6 0;
v000001437439fd30_0 .var "buf_wr_idx", 6 0;
v000001437439ff10_0 .var "captured_count", 6 0;
v000001437439fe70_0 .net/s "cfo_eps_hat", 15 0, v00000143743451e0_0;  1 drivers
v000001437439fc90_0 .net "cfo_est_valid", 0 0, v0000014374345460_0;  1 drivers
v000001437439fdd0_0 .var "cfo_ready", 0 0;
v000001437439ffb0_0 .net "clk", 0 0, v00000143743a3ba0_0;  1 drivers
v000001437439f970_0 .var "collected_done", 0 0;
v000001437439fa10_0 .var "collecting", 0 0;
v000001437439fab0_0 .net "cpe_out_valid", 0 0, v00000143743851e0_0;  1 drivers
v000001437439fb50_0 .net/s "cpe_phase_err", 15 0, v00000143743856e0_0;  1 drivers
v000001437439fbf0_0 .net/s "cpe_phase_err_tap", 15 0, L_00000143743047a0;  alias, 1 drivers
v0000014374398710_0 .net "cpe_phase_valid", 0 0, v0000014374384740_0;  1 drivers
v00000143743988f0_0 .net "cpe_phase_valid_tap", 0 0, L_0000014374303930;  alias, 1 drivers
v0000014374399a70_0 .var "dbg_cpe_cnt", 15 0;
v0000014374399e30_0 .var "dbg_fft_in_cnt", 15 0;
v0000014374399bb0_0 .var/i "dbg_fft_in_file", 31 0;
v0000014374398990_0 .var "dbg_fft_in_idx", 6 0;
v0000014374399cf0_0 .var "dbg_fft_out_cnt", 15 0;
v0000014374399430_0 .var "dbg_in_cnt", 15 0;
v0000014374398fd0_0 .var "dbg_zf_cnt", 15 0;
v0000014374399890_0 .net "fft1_done", 0 0, v0000014374389b40_0;  1 drivers
v000001437439a3d0_0 .var/s "fft1_im_r", 15 0;
v0000014374398350_0 .net/s "fft1_out_im", 15 0, L_0000014374304490;  1 drivers
v0000014374399070_0 .net/s "fft1_out_re", 15 0, L_00000143743033f0;  1 drivers
v0000014374398490_0 .var/s "fft1_re_r", 15 0;
v0000014374398530_0 .net "fft2_done", 0 0, v000001437438a450_0;  1 drivers
v00000143743983f0_0 .var/s "fft2_im_r", 15 0;
v0000014374399f70_0 .net/s "fft2_out_im", 15 0, L_00000143743048f0;  1 drivers
v0000014374398df0_0 .net/s "fft2_out_re", 15 0, L_0000014374303540;  1 drivers
v0000014374399390_0 .var/s "fft2_re_r", 15 0;
v0000014374399ed0_0 .var "fft_data_valid_d", 0 0;
v0000014374398b70_0 .var "fft_done_latched", 0 0;
v00000143743985d0_0 .var "fft_done_pending", 0 0;
v000001437439a830_0 .net "fft_load_valid", 0 0, L_0000014374303070;  1 drivers
v000001437439a010_0 .var "fft_read_addr", 5 0;
v0000014374398a30_0 .var "fft_read_en", 0 0;
v0000014374398210_0 .net/s "h00_im", 15 0, v00000143743a37e0_0;  1 drivers
v000001437439a150_0 .net/s "h00_re", 15 0, v00000143743a46e0_0;  1 drivers
v0000014374399610_0 .net/s "h01_im", 15 0, v00000143743a4960_0;  1 drivers
v0000014374398ad0_0 .net/s "h01_re", 15 0, v00000143743a2980_0;  1 drivers
v000001437439a290_0 .net/s "h10_im", 15 0, v00000143743a4fa0_0;  1 drivers
v000001437439a5b0_0 .net/s "h10_re", 15 0, v00000143743a3100_0;  1 drivers
v000001437439a330_0 .net/s "h11_im", 15 0, v00000143743a3c40_0;  1 drivers
v00000143743987b0_0 .net/s "h11_re", 15 0, v00000143743a3880_0;  1 drivers
v000001437439a650_0 .net "in_valid", 0 0, v00000143743a4780_0;  1 drivers
v0000014374398e90_0 .net/s "nco_acc_tap", 15 0, L_0000014374303fc0;  alias, 1 drivers
v0000014374399110_0 .net/s "nco_phase", 15 0, v000001437438bb70_0;  1 drivers
v00000143743982b0_0 .net "out_valid", 0 0, v0000014374388060_0;  alias, 1 drivers
v000001437439a0b0_0 .var "play_len", 6 0;
v0000014374398670_0 .var "playing", 0 0;
v000001437439a470_0 .var "playing_d", 0 0;
v000001437439a510_0 .net/s "rot1_im", 15 0, v000001437438d150_0;  1 drivers
v0000014374398850_0 .net/s "rot1_re", 15 0, v000001437438dd30_0;  1 drivers
v0000014374398c10_0 .net/s "rot2_im", 15 0, v000001437438db50_0;  1 drivers
v0000014374398cb0_0 .net/s "rot2_re", 15 0, v000001437438d1f0_0;  1 drivers
v0000014374398d50_0 .var/s "rot_in1_im", 15 0;
v0000014374399d90_0 .var/s "rot_in1_re", 15 0;
v00000143743992f0_0 .var/s "rot_in2_im", 15 0;
v000001437439a1f0_0 .var/s "rot_in2_re", 15 0;
v00000143743991b0_0 .var "rot_in_valid", 0 0;
v0000014374398f30_0 .net/s "rot_phase", 15 0, L_0000014374304570;  1 drivers
v000001437439a6f0_0 .net "rot_valid", 0 0, v0000014374390970_0;  1 drivers
v000001437439a790_0 .net "rst_n", 0 0, v00000143743a4820_0;  1 drivers
v00000143743994d0_0 .net "rx_bits", 3 0, v00000143743878e0_0;  alias, 1 drivers
v0000014374399250_0 .var "state_read", 2 0;
v0000014374399930_0 .var "sym_sample_idx", 6 0;
v0000014374399570_0 .net/s "sync1_im", 15 0, v0000014374394200_0;  1 drivers
v00000143743996b0_0 .net/s "sync1_re", 15 0, v0000014374396820_0;  1 drivers
v0000014374399c50_0 .net/s "sync2_im", 15 0, v0000014374395100_0;  1 drivers
v0000014374399750_0 .net/s "sync2_re", 15 0, v00000143743963c0_0;  1 drivers
v00000143743997f0_0 .net "sync_symbol_start", 0 0, v00000143743947a0_0;  1 drivers
v00000143743999d0_0 .net "sync_valid", 0 0, v0000014374396500_0;  1 drivers
v000001437439a8d0_0 .net "zf_valid_out", 0 0, v000001437439db70_0;  1 drivers
v0000014374399b10_0 .net "zf_valid_tap", 0 0, L_00000143743031c0;  alias, 1 drivers
v0000014374398170_0 .net/s "zf_x1_im_tap", 15 0, L_0000014374304ab0;  alias, 1 drivers
v00000143743a4000_0 .net/s "zf_x1_re_tap", 15 0, L_0000014374303ee0;  alias, 1 drivers
v00000143743a3ce0_0 .net/s "zf_x2_im_tap", 15 0, L_0000014374304110;  alias, 1 drivers
v00000143743a2ac0_0 .net/s "zf_x2_re_tap", 15 0, L_0000014374304b90;  alias, 1 drivers
L_00000143744087e0 .concat [ 7 25 0 0], v0000014374399930_0, L_00000143743a93c8;
L_0000014374408060 .cmp/gt 32, L_00000143744087e0, L_00000143743a9410;
L_0000014374407e80 .concat [ 7 25 0 0], v0000014374399930_0, L_00000143743a9458;
L_00000143744073e0 .cmp/gt 32, L_00000143743a94a0, L_0000014374407e80;
S_0000014374322e10 .scope module, "u_cfo_est" "cfo_estimator_cp_mrc" 4 63, 5 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "in_valid";
    .port_info 3 /INPUT 1 "symbol_start";
    .port_info 4 /INPUT 16 "rx1_re";
    .port_info 5 /INPUT 16 "rx1_im";
    .port_info 6 /INPUT 16 "rx2_re";
    .port_info 7 /INPUT 16 "rx2_im";
    .port_info 8 /OUTPUT 1 "cfo_valid";
    .port_info 9 /OUTPUT 16 "cfo_eps_hat";
P_0000014374305910 .param/l "DATA_W" 0 5 2, +C4<00000000000000000000000000010000>;
P_0000014374305948 .param/l "INV_TWO_PI_Q" 1 5 171, +C4<0000000110000101>;
P_0000014374305980 .param/l "NCP" 0 5 4, +C4<00000000000000000000000000010000>;
P_00000143743059b8 .param/l "NFFT" 0 5 3, +C4<00000000000000000000000001000000>;
L_0000014374304b20 .functor BUFZ 6, v00000143743819e0_0, C4<000000>, C4<000000>, C4<000000>;
v0000014374344380_0 .net/s *"_ivl_10", 16 0, L_00000143743a1f80;  1 drivers
v00000143743453c0_0 .net/s *"_ivl_12", 16 0, L_00000143743a2020;  1 drivers
v0000014374344e20_0 .net/s *"_ivl_16", 16 0, L_00000143743a0180;  1 drivers
v0000014374343ac0_0 .net/s *"_ivl_18", 16 0, L_00000143743a02c0;  1 drivers
L_00000143743a8768 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374343980_0 .net *"_ivl_2", 15 0, L_00000143743a8768;  1 drivers
v0000014374345640_0 .net/s *"_ivl_22", 31 0, L_00000143743a05e0;  1 drivers
L_00000143743a87f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374344c40_0 .net *"_ivl_24", 31 0, L_00000143743a87f8;  1 drivers
v0000014374343d40_0 .net *"_ivl_27", 31 0, L_00000143743a0860;  1 drivers
L_00000143743a8840 .functor BUFT 1, C4<00000000000000000000000110000101>, C4<0>, C4<0>, C4<0>;
v0000014374343de0_0 .net/2s *"_ivl_28", 31 0, L_00000143743a8840;  1 drivers
v0000014374343f20_0 .net *"_ivl_32", 31 0, L_0000014374406ee0;  1 drivers
v0000014374344100_0 .net *"_ivl_34", 20 0, L_0000014374407840;  1 drivers
v0000014374344ec0_0 .net *"_ivl_38", 31 0, L_0000014374406800;  1 drivers
v0000014374343b60_0 .net *"_ivl_40", 27 0, L_0000014374407de0;  1 drivers
v0000014374343e80_0 .net *"_ivl_44", 31 0, L_0000014374408740;  1 drivers
v00000143743455a0_0 .net *"_ivl_46", 27 0, L_0000014374407f20;  1 drivers
L_00000143743a87b0 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374344880_0 .net *"_ivl_6", 15 0, L_00000143743a87b0;  1 drivers
v0000014374345140_0 .var "acc_done", 0 0;
v0000014374345500_0 .var/s "acc_im", 31 0;
v0000014374344560_0 .var/s "acc_re", 31 0;
v0000014374343fc0_0 .net/s "angle_out", 15 0, v0000014374345320_0;  1 drivers
v0000014374345000_0 .var/s "c_r1_im", 15 0;
v00000143743450a0_0 .var/s "c_r1_re", 15 0;
v0000014374344420_0 .var/s "c_r2_im", 15 0;
v00000143743444c0_0 .var/s "c_r2_re", 15 0;
v00000143743451e0_0 .var/s "cfo_eps_hat", 15 0;
v0000014374345460_0 .var "cfo_valid", 0 0;
v00000143743456e0_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v0000014374344a60_0 .net/s "cordic_in_im", 15 0, L_0000014374406e40;  1 drivers
v0000014374345280_0 .net/s "cordic_in_re", 15 0, L_0000014374407160;  1 drivers
v0000014374343840_0 .var/s "d_r1_im", 15 0;
v0000014374344600_0 .var/s "d_r1_re", 15 0;
v0000014374343a20_0 .var/s "d_r2_im", 15 0;
v0000014374344060_0 .var/s "d_r2_re", 15 0;
v00000143743441a0_0 .net/s "eps_hat_q", 15 0, L_0000014374408380;  1 drivers
v00000143743446a0_0 .net/s "eps_mul", 31 0, L_0000014374407480;  1 drivers
v0000014374344740 .array/s "fifo_r1_im", 63 0, 15 0;
v0000014374344920 .array/s "fifo_r1_re", 63 0, 15 0;
v00000143743449c0 .array/s "fifo_r2_im", 63 0, 15 0;
v0000014374380cc0 .array/s "fifo_r2_re", 63 0, 15 0;
v0000014374381760_0 .net "in_valid", 0 0, v0000014374396500_0;  alias, 1 drivers
v0000014374381800_0 .var/i "k", 31 0;
v0000014374380c20_0 .net/s "mrc_im", 16 0, L_00000143743a0400;  1 drivers
v0000014374380b80_0 .net/s "mrc_re", 16 0, L_00000143743a2200;  1 drivers
v0000014374381440_0 .net/s "p1_im", 15 0, v00000143742e4e10_0;  1 drivers
v0000014374381d00_0 .net/s "p1_re", 15 0, v00000143742e4eb0_0;  1 drivers
v0000014374381ee0_0 .net/s "p2_im", 15 0, v00000143743447e0_0;  1 drivers
v00000143743809a0_0 .net/s "p2_re", 15 0, v0000014374344d80_0;  1 drivers
v0000014374381e40_0 .net "rd_ptr", 5 0, L_0000014374304b20;  1 drivers
v0000014374381260_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
v00000143743816c0_0 .net/s "rx1_im", 15 0, v0000014374394200_0;  alias, 1 drivers
v00000143743818a0_0 .net/s "rx1_re", 15 0, v0000014374396820_0;  alias, 1 drivers
v0000014374381f80_0 .net/s "rx2_im", 15 0, v0000014374395100_0;  alias, 1 drivers
v0000014374381300_0 .net/s "rx2_re", 15 0, v00000143743963c0_0;  alias, 1 drivers
v0000014374380360_0 .var "sample_idx", 6 0;
v0000014374381620_0 .net "symbol_start", 0 0, v00000143743947a0_0;  alias, 1 drivers
v0000014374381940_0 .var "valid_d1", 0 0;
v00000143743819e0_0 .var "wr_ptr", 5 0;
E_00000143742d1690 .event posedge, v00000143743456e0_0;
E_00000143742d2ad0/0 .event negedge, v0000014374381260_0;
E_00000143742d2ad0/1 .event posedge, v00000143743456e0_0;
E_00000143742d2ad0 .event/or E_00000143742d2ad0/0, E_00000143742d2ad0/1;
L_00000143743a28e0 .arith/sub 16, L_00000143743a8768, v0000014374345000_0;
L_00000143743a0540 .arith/sub 16, L_00000143743a87b0, v0000014374344420_0;
L_00000143743a1f80 .extend/s 17, v00000143742e4eb0_0;
L_00000143743a2020 .extend/s 17, v0000014374344d80_0;
L_00000143743a2200 .arith/sum 17, L_00000143743a1f80, L_00000143743a2020;
L_00000143743a0180 .extend/s 17, v00000143742e4e10_0;
L_00000143743a02c0 .extend/s 17, v00000143743447e0_0;
L_00000143743a0400 .arith/sum 17, L_00000143743a0180, L_00000143743a02c0;
L_00000143743a05e0 .extend/s 32, v0000014374345320_0;
L_00000143743a0860 .arith/sub 32, L_00000143743a87f8, L_00000143743a05e0;
L_0000014374407480 .arith/mult 32, L_00000143743a0860, L_00000143743a8840;
L_0000014374407840 .part L_0000014374407480, 11, 21;
L_0000014374406ee0 .extend/s 32, L_0000014374407840;
L_0000014374408380 .part L_0000014374406ee0, 0, 16;
L_0000014374407de0 .part v0000014374344560_0, 4, 28;
L_0000014374406800 .extend/s 32, L_0000014374407de0;
L_0000014374407160 .part L_0000014374406800, 0, 16;
L_0000014374407f20 .part v0000014374345500_0, 4, 28;
L_0000014374408740 .extend/s 32, L_0000014374407f20;
L_0000014374406e40 .part L_0000014374408740, 0, 16;
S_0000014374322960 .scope module, "u_mul1" "complex_mult" 5 106, 6 1 0, S_0000014374322e10;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "a_re";
    .port_info 1 /INPUT 16 "a_im";
    .port_info 2 /INPUT 16 "b_re";
    .port_info 3 /INPUT 16 "b_im";
    .port_info 4 /OUTPUT 16 "p_re";
    .port_info 5 /OUTPUT 16 "p_im";
P_00000143743067b0 .param/l "FRAC" 0 6 3, +C4<00000000000000000000000000001011>;
P_00000143743067e8 .param/l "MAX_VAL" 1 6 28, +C4<0111111111111111>;
P_0000014374306820 .param/l "MIN_VAL" 1 6 29, +C4<1000000000000000>;
P_0000014374306858 .param/l "WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
v00000143742e53b0_0 .net/s *"_ivl_0", 31 0, L_00000143743a0900;  1 drivers
v00000143742e5bd0_0 .net/s *"_ivl_12", 31 0, L_00000143743a2480;  1 drivers
v00000143742e65d0_0 .net/s *"_ivl_14", 31 0, L_00000143743a0b80;  1 drivers
v00000143742e67b0_0 .net/s *"_ivl_18", 31 0, L_00000143743a09a0;  1 drivers
v00000143742e5db0_0 .net/s *"_ivl_2", 31 0, L_00000143743a20c0;  1 drivers
v00000143742e54f0_0 .net/s *"_ivl_20", 31 0, L_00000143743a1d00;  1 drivers
v00000143742e68f0_0 .net/s *"_ivl_24", 32 0, L_00000143743a0fe0;  1 drivers
v00000143742e5130_0 .net/s *"_ivl_26", 32 0, L_00000143743a2160;  1 drivers
v00000143742e6850_0 .net/s *"_ivl_30", 32 0, L_00000143743a1080;  1 drivers
v00000143742e6a30_0 .net/s *"_ivl_32", 32 0, L_00000143743a04a0;  1 drivers
v00000143742e5590_0 .net *"_ivl_38", 21 0, L_00000143743a1da0;  1 drivers
v00000143742e6350_0 .net *"_ivl_42", 21 0, L_00000143743a14e0;  1 drivers
v00000143742e6490_0 .net/s *"_ivl_6", 31 0, L_00000143743a1e40;  1 drivers
v00000143742e5450_0 .net/s *"_ivl_8", 31 0, L_00000143743a1bc0;  1 drivers
v00000143742e4ff0_0 .net/s "a_im", 15 0, v0000014374343840_0;  1 drivers
v00000143742e5810_0 .net/s "a_re", 15 0, v0000014374344600_0;  1 drivers
v00000143742e6ad0_0 .net/s "ac", 31 0, L_00000143743a0e00;  1 drivers
v00000143742e5270_0 .net/s "ad", 31 0, L_00000143743a0ae0;  1 drivers
v00000143742e58b0_0 .net/s "b_im", 15 0, L_00000143743a28e0;  1 drivers
v00000143742e5e50_0 .net/s "b_re", 15 0, v00000143743450a0_0;  1 drivers
v00000143742e6170_0 .net/s "bc", 31 0, L_00000143743a1260;  1 drivers
v00000143742e5950_0 .net/s "bd", 31 0, L_00000143743a0a40;  1 drivers
v00000143742e6b70_0 .net/s "im_long", 32 0, L_00000143743a0c20;  1 drivers
v00000143742e5d10_0 .net/s "im_shifted", 32 0, L_00000143743a0cc0;  1 drivers
v00000143742e4e10_0 .var/s "p_im", 15 0;
v00000143742e4eb0_0 .var/s "p_re", 15 0;
v00000143742e5090_0 .net/s "re_long", 32 0, L_00000143743a2840;  1 drivers
v00000143742e51d0_0 .net/s "re_shifted", 32 0, L_00000143743a1440;  1 drivers
E_00000143742d7190 .event anyedge, v00000143742e51d0_0, v00000143742e5d10_0;
L_00000143743a0900 .extend/s 32, v0000014374344600_0;
L_00000143743a20c0 .extend/s 32, v00000143743450a0_0;
L_00000143743a0e00 .arith/mult 32, L_00000143743a0900, L_00000143743a20c0;
L_00000143743a1e40 .extend/s 32, v0000014374343840_0;
L_00000143743a1bc0 .extend/s 32, L_00000143743a28e0;
L_00000143743a0a40 .arith/mult 32, L_00000143743a1e40, L_00000143743a1bc0;
L_00000143743a2480 .extend/s 32, v0000014374344600_0;
L_00000143743a0b80 .extend/s 32, L_00000143743a28e0;
L_00000143743a0ae0 .arith/mult 32, L_00000143743a2480, L_00000143743a0b80;
L_00000143743a09a0 .extend/s 32, v0000014374343840_0;
L_00000143743a1d00 .extend/s 32, v00000143743450a0_0;
L_00000143743a1260 .arith/mult 32, L_00000143743a09a0, L_00000143743a1d00;
L_00000143743a0fe0 .extend/s 33, L_00000143743a0e00;
L_00000143743a2160 .extend/s 33, L_00000143743a0a40;
L_00000143743a2840 .arith/sub 33, L_00000143743a0fe0, L_00000143743a2160;
L_00000143743a1080 .extend/s 33, L_00000143743a0ae0;
L_00000143743a04a0 .extend/s 33, L_00000143743a1260;
L_00000143743a0c20 .arith/sum 33, L_00000143743a1080, L_00000143743a04a0;
L_00000143743a1da0 .part L_00000143743a2840, 11, 22;
L_00000143743a1440 .extend/s 33, L_00000143743a1da0;
L_00000143743a14e0 .part L_00000143743a0c20, 11, 22;
L_00000143743a0cc0 .extend/s 33, L_00000143743a14e0;
S_00000143743235e0 .scope module, "u_mul2" "complex_mult" 5 114, 6 1 0, S_0000014374322e10;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "a_re";
    .port_info 1 /INPUT 16 "a_im";
    .port_info 2 /INPUT 16 "b_re";
    .port_info 3 /INPUT 16 "b_im";
    .port_info 4 /OUTPUT 16 "p_re";
    .port_info 5 /OUTPUT 16 "p_im";
P_000001437431fb40 .param/l "FRAC" 0 6 3, +C4<00000000000000000000000000001011>;
P_000001437431fb78 .param/l "MAX_VAL" 1 6 28, +C4<0111111111111111>;
P_000001437431fbb0 .param/l "MIN_VAL" 1 6 29, +C4<1000000000000000>;
P_000001437431fbe8 .param/l "WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
v00000143742718b0_0 .net/s *"_ivl_0", 31 0, L_00000143743a0d60;  1 drivers
v00000143742719f0_0 .net/s *"_ivl_12", 31 0, L_00000143743a2700;  1 drivers
v0000014374272030_0 .net/s *"_ivl_14", 31 0, L_00000143743a1760;  1 drivers
v00000143742728f0_0 .net/s *"_ivl_18", 31 0, L_00000143743a11c0;  1 drivers
v0000014374272490_0 .net/s *"_ivl_2", 31 0, L_00000143743a19e0;  1 drivers
v00000143742725d0_0 .net/s *"_ivl_20", 31 0, L_00000143743a2520;  1 drivers
v0000014374272670_0 .net/s *"_ivl_24", 32 0, L_00000143743a0360;  1 drivers
v0000014374272210_0 .net/s *"_ivl_26", 32 0, L_00000143743a1800;  1 drivers
v0000014374280570_0 .net/s *"_ivl_30", 32 0, L_00000143743a18a0;  1 drivers
v000001437427f490_0 .net/s *"_ivl_32", 32 0, L_00000143743a1580;  1 drivers
v000001437427f670_0 .net *"_ivl_38", 21 0, L_00000143743a16c0;  1 drivers
v0000014374280750_0 .net *"_ivl_42", 21 0, L_00000143743a1a80;  1 drivers
v000001437427f710_0 .net/s *"_ivl_6", 31 0, L_00000143743a07c0;  1 drivers
v000001437427fa30_0 .net/s *"_ivl_8", 31 0, L_00000143743a25c0;  1 drivers
v000001437427ff30_0 .net/s "a_im", 15 0, v0000014374343a20_0;  1 drivers
v000001437427ffd0_0 .net/s "a_re", 15 0, v0000014374344060_0;  1 drivers
v000001437422bb30_0 .net/s "ac", 31 0, L_00000143743a1620;  1 drivers
v000001437422bef0_0 .net/s "ad", 31 0, L_00000143743a0ea0;  1 drivers
v000001437422b090_0 .net/s "b_im", 15 0, L_00000143743a0540;  1 drivers
v000001437422b590_0 .net/s "b_re", 15 0, v00000143743444c0_0;  1 drivers
v000001437422b130_0 .net/s "bc", 31 0, L_00000143743a1120;  1 drivers
v000001437422b3b0_0 .net/s "bd", 31 0, L_00000143743a2660;  1 drivers
v00000143742b7970_0 .net/s "im_long", 32 0, L_00000143743a1ee0;  1 drivers
v00000143742b8a50_0 .net/s "im_shifted", 32 0, L_00000143743a1c60;  1 drivers
v00000143743447e0_0 .var/s "p_im", 15 0;
v0000014374344d80_0 .var/s "p_re", 15 0;
v0000014374344240_0 .net/s "re_long", 32 0, L_00000143743a1300;  1 drivers
v0000014374344ba0_0 .net/s "re_shifted", 32 0, L_00000143743a1b20;  1 drivers
E_00000143742d75d0 .event anyedge, v0000014374344ba0_0, v00000143742b8a50_0;
L_00000143743a0d60 .extend/s 32, v0000014374344060_0;
L_00000143743a19e0 .extend/s 32, v00000143743444c0_0;
L_00000143743a1620 .arith/mult 32, L_00000143743a0d60, L_00000143743a19e0;
L_00000143743a07c0 .extend/s 32, v0000014374343a20_0;
L_00000143743a25c0 .extend/s 32, L_00000143743a0540;
L_00000143743a2660 .arith/mult 32, L_00000143743a07c0, L_00000143743a25c0;
L_00000143743a2700 .extend/s 32, v0000014374344060_0;
L_00000143743a1760 .extend/s 32, L_00000143743a0540;
L_00000143743a0ea0 .arith/mult 32, L_00000143743a2700, L_00000143743a1760;
L_00000143743a11c0 .extend/s 32, v0000014374343a20_0;
L_00000143743a2520 .extend/s 32, v00000143743444c0_0;
L_00000143743a1120 .arith/mult 32, L_00000143743a11c0, L_00000143743a2520;
L_00000143743a0360 .extend/s 33, L_00000143743a1620;
L_00000143743a1800 .extend/s 33, L_00000143743a2660;
L_00000143743a1300 .arith/sub 33, L_00000143743a0360, L_00000143743a1800;
L_00000143743a18a0 .extend/s 33, L_00000143743a0ea0;
L_00000143743a1580 .extend/s 33, L_00000143743a1120;
L_00000143743a1ee0 .arith/sum 33, L_00000143743a18a0, L_00000143743a1580;
L_00000143743a16c0 .part L_00000143743a1300, 11, 22;
L_00000143743a1b20 .extend/s 33, L_00000143743a16c0;
L_00000143743a1a80 .part L_00000143743a1ee0, 11, 22;
L_00000143743a1c60 .extend/s 33, L_00000143743a1a80;
S_0000014374322af0 .scope module, "u_vec" "cordic_vectoring" 5 181, 7 1 0, S_0000014374322e10;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "x_in";
    .port_info 1 /INPUT 16 "y_in";
    .port_info 2 /OUTPUT 16 "z_out";
P_00000143742d69d0 .param/l "WIDTH" 0 7 2, +C4<00000000000000000000000000010000>;
L_00000143743a8888 .functor BUFT 1, C4<0000011001001000>, C4<0>, C4<0>, C4<0>;
v0000014374343c00 .array "atan_table", 11 0;
v0000014374343c00_0 .net/s v0000014374343c00 0, 15 0, L_00000143743a8888; 1 drivers
L_00000143743a88d0 .functor BUFT 1, C4<0000001110110101>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_1 .net/s v0000014374343c00 1, 15 0, L_00000143743a88d0; 1 drivers
L_00000143743a8918 .functor BUFT 1, C4<0000000111110101>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_2 .net/s v0000014374343c00 2, 15 0, L_00000143743a8918; 1 drivers
L_00000143743a8960 .functor BUFT 1, C4<0000000011111110>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_3 .net/s v0000014374343c00 3, 15 0, L_00000143743a8960; 1 drivers
L_00000143743a89a8 .functor BUFT 1, C4<0000000001111111>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_4 .net/s v0000014374343c00 4, 15 0, L_00000143743a89a8; 1 drivers
L_00000143743a89f0 .functor BUFT 1, C4<0000000000111111>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_5 .net/s v0000014374343c00 5, 15 0, L_00000143743a89f0; 1 drivers
L_00000143743a8a38 .functor BUFT 1, C4<0000000000011111>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_6 .net/s v0000014374343c00 6, 15 0, L_00000143743a8a38; 1 drivers
L_00000143743a8a80 .functor BUFT 1, C4<0000000000001111>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_7 .net/s v0000014374343c00 7, 15 0, L_00000143743a8a80; 1 drivers
L_00000143743a8ac8 .functor BUFT 1, C4<0000000000000111>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_8 .net/s v0000014374343c00 8, 15 0, L_00000143743a8ac8; 1 drivers
L_00000143743a8b10 .functor BUFT 1, C4<0000000000000011>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_9 .net/s v0000014374343c00 9, 15 0, L_00000143743a8b10; 1 drivers
L_00000143743a8b58 .functor BUFT 1, C4<0000000000000001>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_10 .net/s v0000014374343c00 10, 15 0, L_00000143743a8b58; 1 drivers
L_00000143743a8ba0 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374343c00_11 .net/s v0000014374343c00 11, 15 0, L_00000143743a8ba0; 1 drivers
v00000143743438e0_0 .var/i "i", 31 0;
v0000014374343ca0 .array/s "x", 12 0, 15 0;
v0000014374344b00_0 .net/s "x_in", 15 0, L_0000014374407160;  alias, 1 drivers
v0000014374344f60 .array/s "y", 12 0, 15 0;
v0000014374344ce0_0 .net/s "y_in", 15 0, L_0000014374406e40;  alias, 1 drivers
v00000143743442e0 .array/s "z", 12 0, 15 0;
v0000014374345320_0 .var/s "z_out", 15 0;
v0000014374344f60_0 .array/port v0000014374344f60, 0;
v0000014374344f60_1 .array/port v0000014374344f60, 1;
E_00000143742d7210/0 .event anyedge, v0000014374344b00_0, v0000014374344ce0_0, v0000014374344f60_0, v0000014374344f60_1;
v0000014374344f60_2 .array/port v0000014374344f60, 2;
v0000014374344f60_3 .array/port v0000014374344f60, 3;
v0000014374344f60_4 .array/port v0000014374344f60, 4;
v0000014374344f60_5 .array/port v0000014374344f60, 5;
E_00000143742d7210/1 .event anyedge, v0000014374344f60_2, v0000014374344f60_3, v0000014374344f60_4, v0000014374344f60_5;
v0000014374344f60_6 .array/port v0000014374344f60, 6;
v0000014374344f60_7 .array/port v0000014374344f60, 7;
v0000014374344f60_8 .array/port v0000014374344f60, 8;
v0000014374344f60_9 .array/port v0000014374344f60, 9;
E_00000143742d7210/2 .event anyedge, v0000014374344f60_6, v0000014374344f60_7, v0000014374344f60_8, v0000014374344f60_9;
v0000014374344f60_10 .array/port v0000014374344f60, 10;
v0000014374344f60_11 .array/port v0000014374344f60, 11;
v0000014374344f60_12 .array/port v0000014374344f60, 12;
v0000014374343ca0_0 .array/port v0000014374343ca0, 0;
E_00000143742d7210/3 .event anyedge, v0000014374344f60_10, v0000014374344f60_11, v0000014374344f60_12, v0000014374343ca0_0;
v0000014374343ca0_1 .array/port v0000014374343ca0, 1;
v0000014374343ca0_2 .array/port v0000014374343ca0, 2;
v0000014374343ca0_3 .array/port v0000014374343ca0, 3;
v0000014374343ca0_4 .array/port v0000014374343ca0, 4;
E_00000143742d7210/4 .event anyedge, v0000014374343ca0_1, v0000014374343ca0_2, v0000014374343ca0_3, v0000014374343ca0_4;
v0000014374343ca0_5 .array/port v0000014374343ca0, 5;
v0000014374343ca0_6 .array/port v0000014374343ca0, 6;
v0000014374343ca0_7 .array/port v0000014374343ca0, 7;
v0000014374343ca0_8 .array/port v0000014374343ca0, 8;
E_00000143742d7210/5 .event anyedge, v0000014374343ca0_5, v0000014374343ca0_6, v0000014374343ca0_7, v0000014374343ca0_8;
v0000014374343ca0_9 .array/port v0000014374343ca0, 9;
v0000014374343ca0_10 .array/port v0000014374343ca0, 10;
v0000014374343ca0_11 .array/port v0000014374343ca0, 11;
v0000014374343ca0_12 .array/port v0000014374343ca0, 12;
E_00000143742d7210/6 .event anyedge, v0000014374343ca0_9, v0000014374343ca0_10, v0000014374343ca0_11, v0000014374343ca0_12;
v00000143743442e0_0 .array/port v00000143743442e0, 0;
v00000143743442e0_1 .array/port v00000143743442e0, 1;
v00000143743442e0_2 .array/port v00000143743442e0, 2;
v00000143743442e0_3 .array/port v00000143743442e0, 3;
E_00000143742d7210/7 .event anyedge, v00000143743442e0_0, v00000143743442e0_1, v00000143743442e0_2, v00000143743442e0_3;
v00000143743442e0_4 .array/port v00000143743442e0, 4;
v00000143743442e0_5 .array/port v00000143743442e0, 5;
v00000143743442e0_6 .array/port v00000143743442e0, 6;
v00000143743442e0_7 .array/port v00000143743442e0, 7;
E_00000143742d7210/8 .event anyedge, v00000143743442e0_4, v00000143743442e0_5, v00000143743442e0_6, v00000143743442e0_7;
v00000143743442e0_8 .array/port v00000143743442e0, 8;
v00000143743442e0_9 .array/port v00000143743442e0, 9;
v00000143743442e0_10 .array/port v00000143743442e0, 10;
v00000143743442e0_11 .array/port v00000143743442e0, 11;
E_00000143742d7210/9 .event anyedge, v00000143743442e0_8, v00000143743442e0_9, v00000143743442e0_10, v00000143743442e0_11;
v00000143743442e0_12 .array/port v00000143743442e0, 12;
E_00000143742d7210/10 .event anyedge, v00000143743442e0_12, v0000014374343c00_0, v0000014374343c00_1, v0000014374343c00_2;
E_00000143742d7210/11 .event anyedge, v0000014374343c00_3, v0000014374343c00_4, v0000014374343c00_5, v0000014374343c00_6;
E_00000143742d7210/12 .event anyedge, v0000014374343c00_7, v0000014374343c00_8, v0000014374343c00_9, v0000014374343c00_10;
E_00000143742d7210/13 .event anyedge, v0000014374343c00_11;
E_00000143742d7210 .event/or E_00000143742d7210/0, E_00000143742d7210/1, E_00000143742d7210/2, E_00000143742d7210/3, E_00000143742d7210/4, E_00000143742d7210/5, E_00000143742d7210/6, E_00000143742d7210/7, E_00000143742d7210/8, E_00000143742d7210/9, E_00000143742d7210/10, E_00000143742d7210/11, E_00000143742d7210/12, E_00000143742d7210/13;
S_0000014374322c80 .scope module, "u_cpe" "cpe_tracker" 4 374, 8 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "in_valid";
    .port_info 3 /INPUT 16 "X1_re";
    .port_info 4 /INPUT 16 "X1_im";
    .port_info 5 /INPUT 16 "X2_re";
    .port_info 6 /INPUT 16 "X2_im";
    .port_info 7 /OUTPUT 1 "out_valid";
    .port_info 8 /OUTPUT 16 "X1c_re";
    .port_info 9 /OUTPUT 16 "X1c_im";
    .port_info 10 /OUTPUT 16 "X2c_re";
    .port_info 11 /OUTPUT 16 "X2c_im";
    .port_info 12 /OUTPUT 1 "phase_err_valid";
    .port_info 13 /OUTPUT 16 "phase_err";
P_000001437430cf10 .param/l "DATA_W" 0 8 2, +C4<00000000000000000000000000010000>;
P_000001437430cf48 .param/l "NFFT" 0 8 4, +C4<00000000000000000000000001000000>;
P_000001437430cf80 .param/l "PHASE_W" 0 8 3, +C4<00000000000000000000000000010000>;
P_000001437430cfb8 .param/l "QPSK_45" 1 8 41, +C4<0000011001001000>;
P_000001437430cff0 .param/l "QPSK_45N" 1 8 43, +C4<1111100110111000>;
P_000001437430d028 .param/l "QPSK_90" 1 8 42, +C4<0000110010010001>;
v0000014374384380_0 .net/s "X1_im", 15 0, v000001437439f5b0_0;  alias, 1 drivers
v0000014374385a00_0 .net/s "X1_re", 15 0, v000001437439d210_0;  alias, 1 drivers
v0000014374385aa0_0 .var/s "X1c_im", 15 0;
v0000014374385b40_0 .var/s "X1c_re", 15 0;
v0000014374385140_0 .net/s "X2_im", 15 0, v000001437439d2b0_0;  alias, 1 drivers
v0000014374385be0_0 .net/s "X2_re", 15 0, v000001437439ee30_0;  alias, 1 drivers
v0000014374385c80_0 .var/s "X2c_im", 15 0;
v0000014374385fa0_0 .var/s "X2c_re", 15 0;
L_00000143743a9d58 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374385dc0_0 .net *"_ivl_6", 15 0, L_00000143743a9d58;  1 drivers
v0000014374385d20_0 .net/s "ang1", 15 0, v0000014374385820_0;  1 drivers
v0000014374384f60_0 .net/s "ang2", 15 0, v0000014374385640_0;  1 drivers
v0000014374385000_0 .var/s "avg_err_reg", 15 0;
v00000143743841a0_0 .var "bank", 0 0;
v0000014374385e60_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v00000143743850a0_0 .var "cnt", 5 0;
v0000014374384240_0 .net/s "current_total_diff", 15 0, L_0000014374402480;  1 drivers
v0000014374384920_0 .net/s "diff1", 15 0, L_0000014374402de0;  1 drivers
v00000143743842e0_0 .net/s "diff2", 15 0, L_00000143744023e0;  1 drivers
v0000014374384420_0 .var "first_symbol_done", 0 0;
v00000143743846a0_0 .net "in_valid", 0 0, v000001437439db70_0;  alias, 1 drivers
v00000143743851e0_0 .var "out_valid", 0 0;
v00000143743856e0_0 .var/s "phase_err", 15 0;
v0000014374384740_0 .var "phase_err_valid", 0 0;
v00000143743847e0_0 .var/s "r_x1_im", 15 0;
v0000014374384880_0 .var/s "r_x1_re", 15 0;
v00000143743849c0_0 .var/s "r_x2_im", 15 0;
v0000014374387520_0 .var/s "r_x2_re", 15 0;
v0000014374387840 .array/s "ram_x1_im", 127 0, 15 0;
v0000014374386f80 .array/s "ram_x1_re", 127 0, 15 0;
v0000014374386760 .array/s "ram_x2_im", 127 0, 15 0;
v00000143743884c0 .array/s "ram_x2_re", 127 0, 15 0;
v00000143743869e0_0 .var "read_active", 0 0;
v0000014374386a80_0 .var "read_bank", 0 0;
v0000014374387020_0 .var "read_cnt", 5 0;
v0000014374386440_0 .net/s "rot_angle", 15 0, L_0000014374402520;  1 drivers
v00000143743881a0_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
v00000143743864e0_0 .var/s "sum_err", 31 0;
v0000014374388740_0 .var/s "sum_next", 31 0;
v00000143743875c0_0 .var "valid_d1", 0 0;
v0000014374386260_0 .net/s "x1_fixed_im", 15 0, v00000143743805e0_0;  1 drivers
v0000014374386b20_0 .net/s "x1_fixed_re", 15 0, v00000143743804a0_0;  1 drivers
v0000014374386120_0 .net/s "x2_fixed_im", 15 0, v0000014374385320_0;  1 drivers
v0000014374386580_0 .net/s "x2_fixed_re", 15 0, v0000014374384b00_0;  1 drivers
L_0000014374402de0 .ufunc/vec4 TD_tb_top_receiver.u_top.u_cpe.calc_diff, 16, v0000014374385820_0 (v0000014374380d60_0) S_0000014374322fa0;
L_00000143744023e0 .ufunc/vec4 TD_tb_top_receiver.u_top.u_cpe.calc_diff, 16, v0000014374385640_0 (v0000014374380d60_0) S_0000014374322fa0;
L_0000014374402480 .arith/sum 16, L_0000014374402de0, L_00000143744023e0;
L_0000014374402520 .arith/sub 16, L_00000143743a9d58, v0000014374385000_0;
S_0000014374322fa0 .scope function.vec4.u16, "calc_diff" "calc_diff" 8 46, 8 46 0, S_0000014374322c80;
 .timescale -9 -12;
; Variable calc_diff is vec4 return value of scope S_0000014374322fa0
v0000014374380d60_0 .var/s "theta", 15 0;
v0000014374381a80_0 .var/s "tmp", 15 0;
TD_tb_top_receiver.u_top.u_cpe.calc_diff ;
    %load/vec4 v0000014374380d60_0;
    %subi 1608, 0, 16;
    %store/vec4 v0000014374381a80_0, 0, 16;
    %load/vec4 v0000014374381a80_0;
    %cmpi/s 1608, 0, 16;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_1.2, 5;
    %load/vec4 v0000014374381a80_0;
    %subi 3217, 0, 16;
    %store/vec4 v0000014374381a80_0, 0, 16;
T_1.2 ;
    %load/vec4 v0000014374381a80_0;
    %cmpi/s 1608, 0, 16;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_1.4, 5;
    %load/vec4 v0000014374381a80_0;
    %subi 3217, 0, 16;
    %store/vec4 v0000014374381a80_0, 0, 16;
T_1.4 ;
    %load/vec4 v0000014374381a80_0;
    %cmpi/s 1608, 0, 16;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_1.6, 5;
    %load/vec4 v0000014374381a80_0;
    %subi 3217, 0, 16;
    %store/vec4 v0000014374381a80_0, 0, 16;
T_1.6 ;
    %load/vec4 v0000014374381a80_0;
    %cmpi/s 63928, 0, 16;
    %jmp/0xz  T_1.8, 5;
    %load/vec4 v0000014374381a80_0;
    %addi 3217, 0, 16;
    %store/vec4 v0000014374381a80_0, 0, 16;
T_1.8 ;
    %load/vec4 v0000014374381a80_0;
    %cmpi/s 63928, 0, 16;
    %jmp/0xz  T_1.10, 5;
    %load/vec4 v0000014374381a80_0;
    %addi 3217, 0, 16;
    %store/vec4 v0000014374381a80_0, 0, 16;
T_1.10 ;
    %load/vec4 v0000014374381a80_0;
    %cmpi/s 63928, 0, 16;
    %jmp/0xz  T_1.12, 5;
    %load/vec4 v0000014374381a80_0;
    %addi 3217, 0, 16;
    %store/vec4 v0000014374381a80_0, 0, 16;
T_1.12 ;
    %load/vec4 v0000014374381a80_0;
    %ret/vec4 0, 0, 16;  Assign to calc_diff (store_vec4_to_lval)
    %end;
S_0000014374383d10 .scope module, "u_rot1" "cordic_rotator" 8 199, 9 1 0, S_0000014374322c80;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 16 "x_in";
    .port_info 3 /INPUT 16 "y_in";
    .port_info 4 /INPUT 16 "theta_in";
    .port_info 5 /OUTPUT 16 "x_out";
    .port_info 6 /OUTPUT 16 "y_out";
P_00000143742d6d90 .param/l "WIDTH" 0 9 2, +C4<00000000000000000000000000010000>;
v0000014374380180_0 .net/s *"_ivl_37", 31 0, L_0000014374403880;  1 drivers
L_00000143743aa100 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v0000014374381da0_0 .net/2s *"_ivl_39", 31 0, L_00000143743aa100;  1 drivers
v0000014374380f40_0 .net/s *"_ivl_44", 31 0, L_0000014374402e80;  1 drivers
L_00000143743aa148 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v0000014374381580_0 .net/2s *"_ivl_46", 31 0, L_00000143743aa148;  1 drivers
L_00000143743a9da0 .functor BUFT 1, C4<0000011001001000>, C4<0>, C4<0>, C4<0>;
v0000014374380400 .array "atan_table", 11 0;
v0000014374380400_0 .net/s v0000014374380400 0, 15 0, L_00000143743a9da0; 1 drivers
L_00000143743a9de8 .functor BUFT 1, C4<0000001110110101>, C4<0>, C4<0>, C4<0>;
v0000014374380400_1 .net/s v0000014374380400 1, 15 0, L_00000143743a9de8; 1 drivers
L_00000143743a9e30 .functor BUFT 1, C4<0000000111110101>, C4<0>, C4<0>, C4<0>;
v0000014374380400_2 .net/s v0000014374380400 2, 15 0, L_00000143743a9e30; 1 drivers
L_00000143743a9e78 .functor BUFT 1, C4<0000000011111110>, C4<0>, C4<0>, C4<0>;
v0000014374380400_3 .net/s v0000014374380400 3, 15 0, L_00000143743a9e78; 1 drivers
L_00000143743a9ec0 .functor BUFT 1, C4<0000000001111111>, C4<0>, C4<0>, C4<0>;
v0000014374380400_4 .net/s v0000014374380400 4, 15 0, L_00000143743a9ec0; 1 drivers
L_00000143743a9f08 .functor BUFT 1, C4<0000000000111111>, C4<0>, C4<0>, C4<0>;
v0000014374380400_5 .net/s v0000014374380400 5, 15 0, L_00000143743a9f08; 1 drivers
L_00000143743a9f50 .functor BUFT 1, C4<0000000000011111>, C4<0>, C4<0>, C4<0>;
v0000014374380400_6 .net/s v0000014374380400 6, 15 0, L_00000143743a9f50; 1 drivers
L_00000143743a9f98 .functor BUFT 1, C4<0000000000001111>, C4<0>, C4<0>, C4<0>;
v0000014374380400_7 .net/s v0000014374380400 7, 15 0, L_00000143743a9f98; 1 drivers
L_00000143743a9fe0 .functor BUFT 1, C4<0000000000000111>, C4<0>, C4<0>, C4<0>;
v0000014374380400_8 .net/s v0000014374380400 8, 15 0, L_00000143743a9fe0; 1 drivers
L_00000143743aa028 .functor BUFT 1, C4<0000000000000011>, C4<0>, C4<0>, C4<0>;
v0000014374380400_9 .net/s v0000014374380400 9, 15 0, L_00000143743aa028; 1 drivers
L_00000143743aa070 .functor BUFT 1, C4<0000000000000001>, C4<0>, C4<0>, C4<0>;
v0000014374380400_10 .net/s v0000014374380400 10, 15 0, L_00000143743aa070; 1 drivers
L_00000143743aa0b8 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374380400_11 .net/s v0000014374380400 11, 15 0, L_00000143743aa0b8; 1 drivers
o0000014374352578 .functor BUFZ 1, C4<z>; HiZ drive
v0000014374381b20_0 .net "clk", 0 0, o0000014374352578;  0 drivers
v0000014374381bc0_0 .var/i "i", 31 0;
o00000143743525d8 .functor BUFZ 1, C4<z>; HiZ drive
v0000014374380220_0 .net "rst_n", 0 0, o00000143743525d8;  0 drivers
v0000014374381c60_0 .net/s "theta_in", 15 0, L_0000014374402520;  alias, 1 drivers
v0000014374380e00 .array/s "x", 12 0, 15 0;
v00000143743802c0_0 .net/s "x_in", 15 0, v0000014374384880_0;  1 drivers
v00000143743804a0_0 .var/s "x_out", 15 0;
v00000143743811c0_0 .net/s "x_scaled", 31 0, L_0000014374402ca0;  1 drivers
v0000014374380540 .array/s "y", 12 0, 15 0;
v0000014374380ea0_0 .net/s "y_in", 15 0, v00000143743847e0_0;  1 drivers
v00000143743805e0_0 .var/s "y_out", 15 0;
v0000014374380680_0 .net/s "y_scaled", 31 0, L_0000014374401300;  1 drivers
v00000143743813a0 .array/s "z", 12 0, 15 0;
E_00000143742d6a90 .event anyedge, v00000143743811c0_0, v0000014374380680_0;
v00000143743813a0_0 .array/port v00000143743813a0, 0;
E_00000143742d7390/0 .event anyedge, v00000143743802c0_0, v0000014374380ea0_0, v0000014374381c60_0, v00000143743813a0_0;
v00000143743813a0_1 .array/port v00000143743813a0, 1;
v00000143743813a0_2 .array/port v00000143743813a0, 2;
v00000143743813a0_3 .array/port v00000143743813a0, 3;
v00000143743813a0_4 .array/port v00000143743813a0, 4;
E_00000143742d7390/1 .event anyedge, v00000143743813a0_1, v00000143743813a0_2, v00000143743813a0_3, v00000143743813a0_4;
v00000143743813a0_5 .array/port v00000143743813a0, 5;
v00000143743813a0_6 .array/port v00000143743813a0, 6;
v00000143743813a0_7 .array/port v00000143743813a0, 7;
v00000143743813a0_8 .array/port v00000143743813a0, 8;
E_00000143742d7390/2 .event anyedge, v00000143743813a0_5, v00000143743813a0_6, v00000143743813a0_7, v00000143743813a0_8;
v00000143743813a0_9 .array/port v00000143743813a0, 9;
v00000143743813a0_10 .array/port v00000143743813a0, 10;
v00000143743813a0_11 .array/port v00000143743813a0, 11;
v00000143743813a0_12 .array/port v00000143743813a0, 12;
E_00000143742d7390/3 .event anyedge, v00000143743813a0_9, v00000143743813a0_10, v00000143743813a0_11, v00000143743813a0_12;
v0000014374380e00_0 .array/port v0000014374380e00, 0;
v0000014374380e00_1 .array/port v0000014374380e00, 1;
v0000014374380e00_2 .array/port v0000014374380e00, 2;
v0000014374380e00_3 .array/port v0000014374380e00, 3;
E_00000143742d7390/4 .event anyedge, v0000014374380e00_0, v0000014374380e00_1, v0000014374380e00_2, v0000014374380e00_3;
v0000014374380e00_4 .array/port v0000014374380e00, 4;
v0000014374380e00_5 .array/port v0000014374380e00, 5;
v0000014374380e00_6 .array/port v0000014374380e00, 6;
v0000014374380e00_7 .array/port v0000014374380e00, 7;
E_00000143742d7390/5 .event anyedge, v0000014374380e00_4, v0000014374380e00_5, v0000014374380e00_6, v0000014374380e00_7;
v0000014374380e00_8 .array/port v0000014374380e00, 8;
v0000014374380e00_9 .array/port v0000014374380e00, 9;
v0000014374380e00_10 .array/port v0000014374380e00, 10;
v0000014374380e00_11 .array/port v0000014374380e00, 11;
E_00000143742d7390/6 .event anyedge, v0000014374380e00_8, v0000014374380e00_9, v0000014374380e00_10, v0000014374380e00_11;
v0000014374380e00_12 .array/port v0000014374380e00, 12;
v0000014374380540_0 .array/port v0000014374380540, 0;
v0000014374380540_1 .array/port v0000014374380540, 1;
v0000014374380540_2 .array/port v0000014374380540, 2;
E_00000143742d7390/7 .event anyedge, v0000014374380e00_12, v0000014374380540_0, v0000014374380540_1, v0000014374380540_2;
v0000014374380540_3 .array/port v0000014374380540, 3;
v0000014374380540_4 .array/port v0000014374380540, 4;
v0000014374380540_5 .array/port v0000014374380540, 5;
v0000014374380540_6 .array/port v0000014374380540, 6;
E_00000143742d7390/8 .event anyedge, v0000014374380540_3, v0000014374380540_4, v0000014374380540_5, v0000014374380540_6;
v0000014374380540_7 .array/port v0000014374380540, 7;
v0000014374380540_8 .array/port v0000014374380540, 8;
v0000014374380540_9 .array/port v0000014374380540, 9;
v0000014374380540_10 .array/port v0000014374380540, 10;
E_00000143742d7390/9 .event anyedge, v0000014374380540_7, v0000014374380540_8, v0000014374380540_9, v0000014374380540_10;
v0000014374380540_11 .array/port v0000014374380540, 11;
v0000014374380540_12 .array/port v0000014374380540, 12;
E_00000143742d7390/10 .event anyedge, v0000014374380540_11, v0000014374380540_12, v0000014374380400_0, v0000014374380400_1;
E_00000143742d7390/11 .event anyedge, v0000014374380400_2, v0000014374380400_3, v0000014374380400_4, v0000014374380400_5;
E_00000143742d7390/12 .event anyedge, v0000014374380400_6, v0000014374380400_7, v0000014374380400_8, v0000014374380400_9;
E_00000143742d7390/13 .event anyedge, v0000014374380400_10, v0000014374380400_11;
E_00000143742d7390 .event/or E_00000143742d7390/0, E_00000143742d7390/1, E_00000143742d7390/2, E_00000143742d7390/3, E_00000143742d7390/4, E_00000143742d7390/5, E_00000143742d7390/6, E_00000143742d7390/7, E_00000143742d7390/8, E_00000143742d7390/9, E_00000143742d7390/10, E_00000143742d7390/11, E_00000143742d7390/12, E_00000143742d7390/13;
L_0000014374403880 .extend/s 32, v0000014374380e00_12;
L_0000014374402ca0 .arith/mult 32, L_0000014374403880, L_00000143743aa100;
L_0000014374402e80 .extend/s 32, v0000014374380540_12;
L_0000014374401300 .arith/mult 32, L_0000014374402e80, L_00000143743aa148;
S_00000143743836d0 .scope module, "u_rot2" "cordic_rotator" 8 204, 9 1 0, S_0000014374322c80;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 16 "x_in";
    .port_info 3 /INPUT 16 "y_in";
    .port_info 4 /INPUT 16 "theta_in";
    .port_info 5 /OUTPUT 16 "x_out";
    .port_info 6 /OUTPUT 16 "y_out";
P_00000143742d6a10 .param/l "WIDTH" 0 9 2, +C4<00000000000000000000000000010000>;
v0000014374380720_0 .net/s *"_ivl_37", 31 0, L_0000014374402660;  1 drivers
L_00000143743aa4f0 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v00000143743807c0_0 .net/2s *"_ivl_39", 31 0, L_00000143743aa4f0;  1 drivers
v0000014374380860_0 .net/s *"_ivl_44", 31 0, L_00000143744013a0;  1 drivers
L_00000143743aa538 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v0000014374380900_0 .net/2s *"_ivl_46", 31 0, L_00000143743aa538;  1 drivers
L_00000143743aa190 .functor BUFT 1, C4<0000011001001000>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0 .array "atan_table", 11 0;
v0000014374380fe0_0 .net/s v0000014374380fe0 0, 15 0, L_00000143743aa190; 1 drivers
L_00000143743aa1d8 .functor BUFT 1, C4<0000001110110101>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_1 .net/s v0000014374380fe0 1, 15 0, L_00000143743aa1d8; 1 drivers
L_00000143743aa220 .functor BUFT 1, C4<0000000111110101>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_2 .net/s v0000014374380fe0 2, 15 0, L_00000143743aa220; 1 drivers
L_00000143743aa268 .functor BUFT 1, C4<0000000011111110>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_3 .net/s v0000014374380fe0 3, 15 0, L_00000143743aa268; 1 drivers
L_00000143743aa2b0 .functor BUFT 1, C4<0000000001111111>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_4 .net/s v0000014374380fe0 4, 15 0, L_00000143743aa2b0; 1 drivers
L_00000143743aa2f8 .functor BUFT 1, C4<0000000000111111>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_5 .net/s v0000014374380fe0 5, 15 0, L_00000143743aa2f8; 1 drivers
L_00000143743aa340 .functor BUFT 1, C4<0000000000011111>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_6 .net/s v0000014374380fe0 6, 15 0, L_00000143743aa340; 1 drivers
L_00000143743aa388 .functor BUFT 1, C4<0000000000001111>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_7 .net/s v0000014374380fe0 7, 15 0, L_00000143743aa388; 1 drivers
L_00000143743aa3d0 .functor BUFT 1, C4<0000000000000111>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_8 .net/s v0000014374380fe0 8, 15 0, L_00000143743aa3d0; 1 drivers
L_00000143743aa418 .functor BUFT 1, C4<0000000000000011>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_9 .net/s v0000014374380fe0 9, 15 0, L_00000143743aa418; 1 drivers
L_00000143743aa460 .functor BUFT 1, C4<0000000000000001>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_10 .net/s v0000014374380fe0 10, 15 0, L_00000143743aa460; 1 drivers
L_00000143743aa4a8 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374380fe0_11 .net/s v0000014374380fe0 11, 15 0, L_00000143743aa4a8; 1 drivers
o00000143743532f8 .functor BUFZ 1, C4<z>; HiZ drive
v0000014374380a40_0 .net "clk", 0 0, o00000143743532f8;  0 drivers
v0000014374380ae0_0 .var/i "i", 31 0;
o0000014374353358 .functor BUFZ 1, C4<z>; HiZ drive
v0000014374381080_0 .net "rst_n", 0 0, o0000014374353358;  0 drivers
v0000014374381120_0 .net/s "theta_in", 15 0, L_0000014374402520;  alias, 1 drivers
v00000143743814e0 .array/s "x", 12 0, 15 0;
v00000143743858c0_0 .net/s "x_in", 15 0, v0000014374387520_0;  1 drivers
v0000014374384b00_0 .var/s "x_out", 15 0;
v0000014374384ba0_0 .net/s "x_scaled", 31 0, L_0000014374401a80;  1 drivers
v0000014374384100 .array/s "y", 12 0, 15 0;
v0000014374384ce0_0 .net/s "y_in", 15 0, v00000143743849c0_0;  1 drivers
v0000014374385320_0 .var/s "y_out", 15 0;
v0000014374384a60_0 .net/s "y_scaled", 31 0, L_0000014374402f20;  1 drivers
v0000014374385460 .array/s "z", 12 0, 15 0;
E_00000143742d6f90 .event anyedge, v0000014374384ba0_0, v0000014374384a60_0;
v0000014374385460_0 .array/port v0000014374385460, 0;
E_00000143742d66d0/0 .event anyedge, v00000143743858c0_0, v0000014374384ce0_0, v0000014374381c60_0, v0000014374385460_0;
v0000014374385460_1 .array/port v0000014374385460, 1;
v0000014374385460_2 .array/port v0000014374385460, 2;
v0000014374385460_3 .array/port v0000014374385460, 3;
v0000014374385460_4 .array/port v0000014374385460, 4;
E_00000143742d66d0/1 .event anyedge, v0000014374385460_1, v0000014374385460_2, v0000014374385460_3, v0000014374385460_4;
v0000014374385460_5 .array/port v0000014374385460, 5;
v0000014374385460_6 .array/port v0000014374385460, 6;
v0000014374385460_7 .array/port v0000014374385460, 7;
v0000014374385460_8 .array/port v0000014374385460, 8;
E_00000143742d66d0/2 .event anyedge, v0000014374385460_5, v0000014374385460_6, v0000014374385460_7, v0000014374385460_8;
v0000014374385460_9 .array/port v0000014374385460, 9;
v0000014374385460_10 .array/port v0000014374385460, 10;
v0000014374385460_11 .array/port v0000014374385460, 11;
v0000014374385460_12 .array/port v0000014374385460, 12;
E_00000143742d66d0/3 .event anyedge, v0000014374385460_9, v0000014374385460_10, v0000014374385460_11, v0000014374385460_12;
v00000143743814e0_0 .array/port v00000143743814e0, 0;
v00000143743814e0_1 .array/port v00000143743814e0, 1;
v00000143743814e0_2 .array/port v00000143743814e0, 2;
v00000143743814e0_3 .array/port v00000143743814e0, 3;
E_00000143742d66d0/4 .event anyedge, v00000143743814e0_0, v00000143743814e0_1, v00000143743814e0_2, v00000143743814e0_3;
v00000143743814e0_4 .array/port v00000143743814e0, 4;
v00000143743814e0_5 .array/port v00000143743814e0, 5;
v00000143743814e0_6 .array/port v00000143743814e0, 6;
v00000143743814e0_7 .array/port v00000143743814e0, 7;
E_00000143742d66d0/5 .event anyedge, v00000143743814e0_4, v00000143743814e0_5, v00000143743814e0_6, v00000143743814e0_7;
v00000143743814e0_8 .array/port v00000143743814e0, 8;
v00000143743814e0_9 .array/port v00000143743814e0, 9;
v00000143743814e0_10 .array/port v00000143743814e0, 10;
v00000143743814e0_11 .array/port v00000143743814e0, 11;
E_00000143742d66d0/6 .event anyedge, v00000143743814e0_8, v00000143743814e0_9, v00000143743814e0_10, v00000143743814e0_11;
v00000143743814e0_12 .array/port v00000143743814e0, 12;
v0000014374384100_0 .array/port v0000014374384100, 0;
v0000014374384100_1 .array/port v0000014374384100, 1;
v0000014374384100_2 .array/port v0000014374384100, 2;
E_00000143742d66d0/7 .event anyedge, v00000143743814e0_12, v0000014374384100_0, v0000014374384100_1, v0000014374384100_2;
v0000014374384100_3 .array/port v0000014374384100, 3;
v0000014374384100_4 .array/port v0000014374384100, 4;
v0000014374384100_5 .array/port v0000014374384100, 5;
v0000014374384100_6 .array/port v0000014374384100, 6;
E_00000143742d66d0/8 .event anyedge, v0000014374384100_3, v0000014374384100_4, v0000014374384100_5, v0000014374384100_6;
v0000014374384100_7 .array/port v0000014374384100, 7;
v0000014374384100_8 .array/port v0000014374384100, 8;
v0000014374384100_9 .array/port v0000014374384100, 9;
v0000014374384100_10 .array/port v0000014374384100, 10;
E_00000143742d66d0/9 .event anyedge, v0000014374384100_7, v0000014374384100_8, v0000014374384100_9, v0000014374384100_10;
v0000014374384100_11 .array/port v0000014374384100, 11;
v0000014374384100_12 .array/port v0000014374384100, 12;
E_00000143742d66d0/10 .event anyedge, v0000014374384100_11, v0000014374384100_12, v0000014374380fe0_0, v0000014374380fe0_1;
E_00000143742d66d0/11 .event anyedge, v0000014374380fe0_2, v0000014374380fe0_3, v0000014374380fe0_4, v0000014374380fe0_5;
E_00000143742d66d0/12 .event anyedge, v0000014374380fe0_6, v0000014374380fe0_7, v0000014374380fe0_8, v0000014374380fe0_9;
E_00000143742d66d0/13 .event anyedge, v0000014374380fe0_10, v0000014374380fe0_11;
E_00000143742d66d0 .event/or E_00000143742d66d0/0, E_00000143742d66d0/1, E_00000143742d66d0/2, E_00000143742d66d0/3, E_00000143742d66d0/4, E_00000143742d66d0/5, E_00000143742d66d0/6, E_00000143742d66d0/7, E_00000143742d66d0/8, E_00000143742d66d0/9, E_00000143742d66d0/10, E_00000143742d66d0/11, E_00000143742d66d0/12, E_00000143742d66d0/13;
L_0000014374402660 .extend/s 32, v00000143743814e0_12;
L_0000014374401a80 .arith/mult 32, L_0000014374402660, L_00000143743aa4f0;
L_00000143744013a0 .extend/s 32, v0000014374384100_12;
L_0000014374402f20 .arith/mult 32, L_00000143744013a0, L_00000143743aa538;
S_0000014374383860 .scope module, "u_vec1" "cordic_vectoring" 8 29, 7 1 0, S_0000014374322c80;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "x_in";
    .port_info 1 /INPUT 16 "y_in";
    .port_info 2 /OUTPUT 16 "z_out";
P_00000143742d6c50 .param/l "WIDTH" 0 7 2, +C4<00000000000000000000000000010000>;
L_00000143743a9698 .functor BUFT 1, C4<0000011001001000>, C4<0>, C4<0>, C4<0>;
v00000143743844c0 .array "atan_table", 11 0;
v00000143743844c0_0 .net/s v00000143743844c0 0, 15 0, L_00000143743a9698; 1 drivers
L_00000143743a96e0 .functor BUFT 1, C4<0000001110110101>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_1 .net/s v00000143743844c0 1, 15 0, L_00000143743a96e0; 1 drivers
L_00000143743a9728 .functor BUFT 1, C4<0000000111110101>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_2 .net/s v00000143743844c0 2, 15 0, L_00000143743a9728; 1 drivers
L_00000143743a9770 .functor BUFT 1, C4<0000000011111110>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_3 .net/s v00000143743844c0 3, 15 0, L_00000143743a9770; 1 drivers
L_00000143743a97b8 .functor BUFT 1, C4<0000000001111111>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_4 .net/s v00000143743844c0 4, 15 0, L_00000143743a97b8; 1 drivers
L_00000143743a9800 .functor BUFT 1, C4<0000000000111111>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_5 .net/s v00000143743844c0 5, 15 0, L_00000143743a9800; 1 drivers
L_00000143743a9848 .functor BUFT 1, C4<0000000000011111>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_6 .net/s v00000143743844c0 6, 15 0, L_00000143743a9848; 1 drivers
L_00000143743a9890 .functor BUFT 1, C4<0000000000001111>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_7 .net/s v00000143743844c0 7, 15 0, L_00000143743a9890; 1 drivers
L_00000143743a98d8 .functor BUFT 1, C4<0000000000000111>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_8 .net/s v00000143743844c0 8, 15 0, L_00000143743a98d8; 1 drivers
L_00000143743a9920 .functor BUFT 1, C4<0000000000000011>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_9 .net/s v00000143743844c0 9, 15 0, L_00000143743a9920; 1 drivers
L_00000143743a9968 .functor BUFT 1, C4<0000000000000001>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_10 .net/s v00000143743844c0 10, 15 0, L_00000143743a9968; 1 drivers
L_00000143743a99b0 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v00000143743844c0_11 .net/s v00000143743844c0 11, 15 0, L_00000143743a99b0; 1 drivers
v0000014374384600_0 .var/i "i", 31 0;
v0000014374384d80 .array/s "x", 12 0, 15 0;
v00000143743853c0_0 .net/s "x_in", 15 0, v000001437439d210_0;  alias, 1 drivers
v0000014374385500 .array/s "y", 12 0, 15 0;
v0000014374385780_0 .net/s "y_in", 15 0, v000001437439f5b0_0;  alias, 1 drivers
v0000014374384e20 .array/s "z", 12 0, 15 0;
v0000014374385820_0 .var/s "z_out", 15 0;
v0000014374385500_0 .array/port v0000014374385500, 0;
v0000014374385500_1 .array/port v0000014374385500, 1;
E_00000143742d6cd0/0 .event anyedge, v00000143743853c0_0, v0000014374385780_0, v0000014374385500_0, v0000014374385500_1;
v0000014374385500_2 .array/port v0000014374385500, 2;
v0000014374385500_3 .array/port v0000014374385500, 3;
v0000014374385500_4 .array/port v0000014374385500, 4;
v0000014374385500_5 .array/port v0000014374385500, 5;
E_00000143742d6cd0/1 .event anyedge, v0000014374385500_2, v0000014374385500_3, v0000014374385500_4, v0000014374385500_5;
v0000014374385500_6 .array/port v0000014374385500, 6;
v0000014374385500_7 .array/port v0000014374385500, 7;
v0000014374385500_8 .array/port v0000014374385500, 8;
v0000014374385500_9 .array/port v0000014374385500, 9;
E_00000143742d6cd0/2 .event anyedge, v0000014374385500_6, v0000014374385500_7, v0000014374385500_8, v0000014374385500_9;
v0000014374385500_10 .array/port v0000014374385500, 10;
v0000014374385500_11 .array/port v0000014374385500, 11;
v0000014374385500_12 .array/port v0000014374385500, 12;
v0000014374384d80_0 .array/port v0000014374384d80, 0;
E_00000143742d6cd0/3 .event anyedge, v0000014374385500_10, v0000014374385500_11, v0000014374385500_12, v0000014374384d80_0;
v0000014374384d80_1 .array/port v0000014374384d80, 1;
v0000014374384d80_2 .array/port v0000014374384d80, 2;
v0000014374384d80_3 .array/port v0000014374384d80, 3;
v0000014374384d80_4 .array/port v0000014374384d80, 4;
E_00000143742d6cd0/4 .event anyedge, v0000014374384d80_1, v0000014374384d80_2, v0000014374384d80_3, v0000014374384d80_4;
v0000014374384d80_5 .array/port v0000014374384d80, 5;
v0000014374384d80_6 .array/port v0000014374384d80, 6;
v0000014374384d80_7 .array/port v0000014374384d80, 7;
v0000014374384d80_8 .array/port v0000014374384d80, 8;
E_00000143742d6cd0/5 .event anyedge, v0000014374384d80_5, v0000014374384d80_6, v0000014374384d80_7, v0000014374384d80_8;
v0000014374384d80_9 .array/port v0000014374384d80, 9;
v0000014374384d80_10 .array/port v0000014374384d80, 10;
v0000014374384d80_11 .array/port v0000014374384d80, 11;
v0000014374384d80_12 .array/port v0000014374384d80, 12;
E_00000143742d6cd0/6 .event anyedge, v0000014374384d80_9, v0000014374384d80_10, v0000014374384d80_11, v0000014374384d80_12;
v0000014374384e20_0 .array/port v0000014374384e20, 0;
v0000014374384e20_1 .array/port v0000014374384e20, 1;
v0000014374384e20_2 .array/port v0000014374384e20, 2;
v0000014374384e20_3 .array/port v0000014374384e20, 3;
E_00000143742d6cd0/7 .event anyedge, v0000014374384e20_0, v0000014374384e20_1, v0000014374384e20_2, v0000014374384e20_3;
v0000014374384e20_4 .array/port v0000014374384e20, 4;
v0000014374384e20_5 .array/port v0000014374384e20, 5;
v0000014374384e20_6 .array/port v0000014374384e20, 6;
v0000014374384e20_7 .array/port v0000014374384e20, 7;
E_00000143742d6cd0/8 .event anyedge, v0000014374384e20_4, v0000014374384e20_5, v0000014374384e20_6, v0000014374384e20_7;
v0000014374384e20_8 .array/port v0000014374384e20, 8;
v0000014374384e20_9 .array/port v0000014374384e20, 9;
v0000014374384e20_10 .array/port v0000014374384e20, 10;
v0000014374384e20_11 .array/port v0000014374384e20, 11;
E_00000143742d6cd0/9 .event anyedge, v0000014374384e20_8, v0000014374384e20_9, v0000014374384e20_10, v0000014374384e20_11;
v0000014374384e20_12 .array/port v0000014374384e20, 12;
E_00000143742d6cd0/10 .event anyedge, v0000014374384e20_12, v00000143743844c0_0, v00000143743844c0_1, v00000143743844c0_2;
E_00000143742d6cd0/11 .event anyedge, v00000143743844c0_3, v00000143743844c0_4, v00000143743844c0_5, v00000143743844c0_6;
E_00000143742d6cd0/12 .event anyedge, v00000143743844c0_7, v00000143743844c0_8, v00000143743844c0_9, v00000143743844c0_10;
E_00000143742d6cd0/13 .event anyedge, v00000143743844c0_11;
E_00000143742d6cd0 .event/or E_00000143742d6cd0/0, E_00000143742d6cd0/1, E_00000143742d6cd0/2, E_00000143742d6cd0/3, E_00000143742d6cd0/4, E_00000143742d6cd0/5, E_00000143742d6cd0/6, E_00000143742d6cd0/7, E_00000143742d6cd0/8, E_00000143742d6cd0/9, E_00000143742d6cd0/10, E_00000143742d6cd0/11, E_00000143742d6cd0/12, E_00000143742d6cd0/13;
S_0000014374382d70 .scope module, "u_vec2" "cordic_vectoring" 8 32, 7 1 0, S_0000014374322c80;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "x_in";
    .port_info 1 /INPUT 16 "y_in";
    .port_info 2 /OUTPUT 16 "z_out";
P_00000143742d6ed0 .param/l "WIDTH" 0 7 2, +C4<00000000000000000000000000010000>;
L_00000143743a99f8 .functor BUFT 1, C4<0000011001001000>, C4<0>, C4<0>, C4<0>;
v0000014374384c40 .array "atan_table", 11 0;
v0000014374384c40_0 .net/s v0000014374384c40 0, 15 0, L_00000143743a99f8; 1 drivers
L_00000143743a9a40 .functor BUFT 1, C4<0000001110110101>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_1 .net/s v0000014374384c40 1, 15 0, L_00000143743a9a40; 1 drivers
L_00000143743a9a88 .functor BUFT 1, C4<0000000111110101>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_2 .net/s v0000014374384c40 2, 15 0, L_00000143743a9a88; 1 drivers
L_00000143743a9ad0 .functor BUFT 1, C4<0000000011111110>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_3 .net/s v0000014374384c40 3, 15 0, L_00000143743a9ad0; 1 drivers
L_00000143743a9b18 .functor BUFT 1, C4<0000000001111111>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_4 .net/s v0000014374384c40 4, 15 0, L_00000143743a9b18; 1 drivers
L_00000143743a9b60 .functor BUFT 1, C4<0000000000111111>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_5 .net/s v0000014374384c40 5, 15 0, L_00000143743a9b60; 1 drivers
L_00000143743a9ba8 .functor BUFT 1, C4<0000000000011111>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_6 .net/s v0000014374384c40 6, 15 0, L_00000143743a9ba8; 1 drivers
L_00000143743a9bf0 .functor BUFT 1, C4<0000000000001111>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_7 .net/s v0000014374384c40 7, 15 0, L_00000143743a9bf0; 1 drivers
L_00000143743a9c38 .functor BUFT 1, C4<0000000000000111>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_8 .net/s v0000014374384c40 8, 15 0, L_00000143743a9c38; 1 drivers
L_00000143743a9c80 .functor BUFT 1, C4<0000000000000011>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_9 .net/s v0000014374384c40 9, 15 0, L_00000143743a9c80; 1 drivers
L_00000143743a9cc8 .functor BUFT 1, C4<0000000000000001>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_10 .net/s v0000014374384c40 10, 15 0, L_00000143743a9cc8; 1 drivers
L_00000143743a9d10 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374384c40_11 .net/s v0000014374384c40 11, 15 0, L_00000143743a9d10; 1 drivers
v0000014374385280_0 .var/i "i", 31 0;
v0000014374384ec0 .array/s "x", 12 0, 15 0;
v0000014374385f00_0 .net/s "x_in", 15 0, v000001437439ee30_0;  alias, 1 drivers
v00000143743855a0 .array/s "y", 12 0, 15 0;
v0000014374384560_0 .net/s "y_in", 15 0, v000001437439d2b0_0;  alias, 1 drivers
v0000014374385960 .array/s "z", 12 0, 15 0;
v0000014374385640_0 .var/s "z_out", 15 0;
v00000143743855a0_0 .array/port v00000143743855a0, 0;
v00000143743855a0_1 .array/port v00000143743855a0, 1;
E_00000143742d6f10/0 .event anyedge, v0000014374385f00_0, v0000014374384560_0, v00000143743855a0_0, v00000143743855a0_1;
v00000143743855a0_2 .array/port v00000143743855a0, 2;
v00000143743855a0_3 .array/port v00000143743855a0, 3;
v00000143743855a0_4 .array/port v00000143743855a0, 4;
v00000143743855a0_5 .array/port v00000143743855a0, 5;
E_00000143742d6f10/1 .event anyedge, v00000143743855a0_2, v00000143743855a0_3, v00000143743855a0_4, v00000143743855a0_5;
v00000143743855a0_6 .array/port v00000143743855a0, 6;
v00000143743855a0_7 .array/port v00000143743855a0, 7;
v00000143743855a0_8 .array/port v00000143743855a0, 8;
v00000143743855a0_9 .array/port v00000143743855a0, 9;
E_00000143742d6f10/2 .event anyedge, v00000143743855a0_6, v00000143743855a0_7, v00000143743855a0_8, v00000143743855a0_9;
v00000143743855a0_10 .array/port v00000143743855a0, 10;
v00000143743855a0_11 .array/port v00000143743855a0, 11;
v00000143743855a0_12 .array/port v00000143743855a0, 12;
v0000014374384ec0_0 .array/port v0000014374384ec0, 0;
E_00000143742d6f10/3 .event anyedge, v00000143743855a0_10, v00000143743855a0_11, v00000143743855a0_12, v0000014374384ec0_0;
v0000014374384ec0_1 .array/port v0000014374384ec0, 1;
v0000014374384ec0_2 .array/port v0000014374384ec0, 2;
v0000014374384ec0_3 .array/port v0000014374384ec0, 3;
v0000014374384ec0_4 .array/port v0000014374384ec0, 4;
E_00000143742d6f10/4 .event anyedge, v0000014374384ec0_1, v0000014374384ec0_2, v0000014374384ec0_3, v0000014374384ec0_4;
v0000014374384ec0_5 .array/port v0000014374384ec0, 5;
v0000014374384ec0_6 .array/port v0000014374384ec0, 6;
v0000014374384ec0_7 .array/port v0000014374384ec0, 7;
v0000014374384ec0_8 .array/port v0000014374384ec0, 8;
E_00000143742d6f10/5 .event anyedge, v0000014374384ec0_5, v0000014374384ec0_6, v0000014374384ec0_7, v0000014374384ec0_8;
v0000014374384ec0_9 .array/port v0000014374384ec0, 9;
v0000014374384ec0_10 .array/port v0000014374384ec0, 10;
v0000014374384ec0_11 .array/port v0000014374384ec0, 11;
v0000014374384ec0_12 .array/port v0000014374384ec0, 12;
E_00000143742d6f10/6 .event anyedge, v0000014374384ec0_9, v0000014374384ec0_10, v0000014374384ec0_11, v0000014374384ec0_12;
v0000014374385960_0 .array/port v0000014374385960, 0;
v0000014374385960_1 .array/port v0000014374385960, 1;
v0000014374385960_2 .array/port v0000014374385960, 2;
v0000014374385960_3 .array/port v0000014374385960, 3;
E_00000143742d6f10/7 .event anyedge, v0000014374385960_0, v0000014374385960_1, v0000014374385960_2, v0000014374385960_3;
v0000014374385960_4 .array/port v0000014374385960, 4;
v0000014374385960_5 .array/port v0000014374385960, 5;
v0000014374385960_6 .array/port v0000014374385960, 6;
v0000014374385960_7 .array/port v0000014374385960, 7;
E_00000143742d6f10/8 .event anyedge, v0000014374385960_4, v0000014374385960_5, v0000014374385960_6, v0000014374385960_7;
v0000014374385960_8 .array/port v0000014374385960, 8;
v0000014374385960_9 .array/port v0000014374385960, 9;
v0000014374385960_10 .array/port v0000014374385960, 10;
v0000014374385960_11 .array/port v0000014374385960, 11;
E_00000143742d6f10/9 .event anyedge, v0000014374385960_8, v0000014374385960_9, v0000014374385960_10, v0000014374385960_11;
v0000014374385960_12 .array/port v0000014374385960, 12;
E_00000143742d6f10/10 .event anyedge, v0000014374385960_12, v0000014374384c40_0, v0000014374384c40_1, v0000014374384c40_2;
E_00000143742d6f10/11 .event anyedge, v0000014374384c40_3, v0000014374384c40_4, v0000014374384c40_5, v0000014374384c40_6;
E_00000143742d6f10/12 .event anyedge, v0000014374384c40_7, v0000014374384c40_8, v0000014374384c40_9, v0000014374384c40_10;
E_00000143742d6f10/13 .event anyedge, v0000014374384c40_11;
E_00000143742d6f10 .event/or E_00000143742d6f10/0, E_00000143742d6f10/1, E_00000143742d6f10/2, E_00000143742d6f10/3, E_00000143742d6f10/4, E_00000143742d6f10/5, E_00000143742d6f10/6, E_00000143742d6f10/7, E_00000143742d6f10/8, E_00000143742d6f10/9, E_00000143742d6f10/10, E_00000143742d6f10/11, E_00000143742d6f10/12, E_00000143742d6f10/13;
S_00000143743828c0 .scope module, "u_demap" "qpsk_demap" 4 395, 10 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "in_valid";
    .port_info 3 /INPUT 16 "X1_re";
    .port_info 4 /INPUT 16 "X1_im";
    .port_info 5 /INPUT 16 "X2_re";
    .port_info 6 /INPUT 16 "X2_im";
    .port_info 7 /OUTPUT 1 "out_valid";
    .port_info 8 /OUTPUT 4 "bits_out";
P_00000143742d7490 .param/l "DATA_W" 0 10 2, +C4<00000000000000000000000000010000>;
v0000014374386ee0_0 .net/s "X1_im", 15 0, v0000014374385aa0_0;  alias, 1 drivers
v00000143743877a0_0 .net/s "X1_re", 15 0, v0000014374385b40_0;  alias, 1 drivers
v0000014374387fc0_0 .net/s "X2_im", 15 0, v0000014374385c80_0;  alias, 1 drivers
v00000143743887e0_0 .net/s "X2_re", 15 0, v0000014374385fa0_0;  alias, 1 drivers
v00000143743878e0_0 .var "bits_out", 3 0;
v0000014374387d40_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v0000014374387ca0_0 .net "in_valid", 0 0, v00000143743851e0_0;  alias, 1 drivers
v0000014374388060_0 .var "out_valid", 0 0;
v0000014374388100_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
S_0000014374382a50 .scope module, "u_fft1" "fft_64pt" 4 258, 11 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "i_start";
    .port_info 3 /OUTPUT 1 "o_done";
    .port_info 4 /INPUT 1 "i_load_valid";
    .port_info 5 /INPUT 16 "i_load_re";
    .port_info 6 /INPUT 16 "i_load_im";
    .port_info 7 /INPUT 6 "i_read_addr";
    .port_info 8 /OUTPUT 16 "o_read_re";
    .port_info 9 /OUTPUT 16 "o_read_im";
L_00000143743033f0 .functor BUFZ 16, L_0000014374407fc0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374304490 .functor BUFZ 16, L_0000014374408880, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
v0000014374387ac0_0 .net *"_ivl_0", 15 0, L_0000014374407fc0;  1 drivers
v0000014374387b60_0 .net *"_ivl_10", 15 0, L_0000014374408880;  1 drivers
v0000014374387c00_0 .net *"_ivl_12", 6 0, L_00000143744066c0;  1 drivers
v0000014374388600_0 .net *"_ivl_14", 8 0, L_0000014374407020;  1 drivers
L_00000143743a9530 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000014374387f20_0 .net *"_ivl_17", 1 0, L_00000143743a9530;  1 drivers
v00000143743886a0_0 .net *"_ivl_2", 6 0, L_0000014374408100;  1 drivers
v0000014374389960_0 .net *"_ivl_4", 8 0, L_0000014374406da0;  1 drivers
L_00000143743a94e8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000014374388920_0 .net *"_ivl_7", 1 0, L_00000143743a94e8;  1 drivers
v0000014374389fa0_0 .var "bank_calc", 0 0;
v0000014374389780_0 .var "bank_in", 0 0;
v0000014374389820_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v0000014374389320_0 .net/s "i_load_im", 15 0, v000001437438d150_0;  alias, 1 drivers
v00000143743896e0_0 .net/s "i_load_re", 15 0, v000001437438dd30_0;  alias, 1 drivers
v00000143743898c0_0 .net "i_load_valid", 0 0, L_0000014374303070;  alias, 1 drivers
v0000014374389000_0 .net "i_read_addr", 5 0, v000001437439a010_0;  1 drivers
L_00000143743a9578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0000014374389f00_0 .net "i_start", 0 0, L_00000143743a9578;  1 drivers
v0000014374388ec0_0 .var "input_ready_pulse", 0 0;
v0000014374389a00_0 .var "load_cnt", 6 0;
v0000014374389aa0 .array/s "mem_im", 127 0, 15 0;
v00000143743889c0 .array/s "mem_re", 127 0, 15 0;
v0000014374389b40_0 .var "o_done", 0 0;
v0000014374389be0_0 .net/s "o_read_im", 15 0, L_0000014374304490;  alias, 1 drivers
v0000014374388c40_0 .net/s "o_read_re", 15 0, L_00000143743033f0;  alias, 1 drivers
v0000014374389c80_0 .var "pending_bank", 0 0;
v0000014374389d20_0 .var "pending_valid", 0 0;
v0000014374389dc0_0 .var "read_hold", 6 0;
v0000014374388f60_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
L_0000014374407fc0 .array/port v00000143743889c0, L_0000014374406da0;
L_0000014374408100 .concat [ 6 1 0 0], v000001437439a010_0, v0000014374389fa0_0;
L_0000014374406da0 .concat [ 7 2 0 0], L_0000014374408100, L_00000143743a94e8;
L_0000014374408880 .array/port v0000014374389aa0, L_0000014374407020;
L_00000143744066c0 .concat [ 6 1 0 0], v000001437439a010_0, v0000014374389fa0_0;
L_0000014374407020 .concat [ 7 2 0 0], L_00000143744066c0, L_00000143743a9530;
S_0000014374382f00 .scope function.vec4.s6, "bit_reverse" "bit_reverse" 11 29, 11 29 0, S_0000014374382a50;
 .timescale -9 -12;
; Variable bit_reverse is vec4 return value of scope S_0000014374382f00
v0000014374388880_0 .var "in", 5 0;
TD_tb_top_receiver.u_top.u_fft1.bit_reverse ;
    %load/vec4 v0000014374388880_0;
    %parti/s 1, 0, 2;
    %load/vec4 v0000014374388880_0;
    %parti/s 1, 1, 2;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374388880_0;
    %parti/s 1, 2, 3;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374388880_0;
    %parti/s 1, 3, 3;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374388880_0;
    %parti/s 1, 4, 4;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374388880_0;
    %parti/s 1, 5, 4;
    %concat/vec4; draw_concat_vec4
    %ret/vec4 0, 0, 6;  Assign to bit_reverse (store_vec4_to_lval)
    %end;
S_0000014374383090 .scope autotask, "run_fft" "run_fft" 11 110, 11 110 0, S_0000014374382a50;
 .timescale -9 -12;
v0000014374387de0 .array/s "buf_im", 63 0, 15 0;
v0000014374386e40 .array/s "buf_re", 63 0, 15 0;
v00000143743861c0_0 .var/i "half", 31 0;
v00000143743873e0_0 .var/i "i", 31 0;
v0000014374386300_0 .var/i "idx", 31 0;
v0000014374386d00_0 .var/i "j", 31 0;
v00000143743882e0_0 .var/i "k", 31 0;
v0000014374387e80_0 .var/i "m", 31 0;
v0000014374388380_0 .var/i "step", 31 0;
v0000014374387660_0 .var/s "t_im", 31 0;
v0000014374386620_0 .var/s "t_re", 31 0;
v0000014374388560_0 .var/s "u_im", 31 0;
v0000014374386da0_0 .var/s "u_re", 31 0;
v00000143743870c0_0 .var/s "w_im", 15 0;
v00000143743863a0_0 .var/s "w_re", 15 0;
v0000014374386800_0 .var "which_bank", 0 0;
TD_tb_top_receiver.u_top.u_fft1.run_fft ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743873e0_0, 0, 32;
T_3.14 ;
    %load/vec4 v00000143743873e0_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_3.15, 5;
    %load/vec4 v0000014374386800_0;
    %load/vec4 v00000143743873e0_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v00000143743889c0, 4;
    %ix/getv/s 4, v00000143743873e0_0;
    %store/vec4a v0000014374386e40, 4, 0;
    %load/vec4 v0000014374386800_0;
    %load/vec4 v00000143743873e0_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v0000014374389aa0, 4;
    %ix/getv/s 4, v00000143743873e0_0;
    %store/vec4a v0000014374387de0, 4, 0;
    %load/vec4 v00000143743873e0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743873e0_0, 0, 32;
    %jmp T_3.14;
T_3.15 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743873e0_0, 0, 32;
T_3.16 ;
    %load/vec4 v00000143743873e0_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_3.17, 5;
    %load/vec4 v00000143743873e0_0;
    %parti/s 6, 0, 2;
    %store/vec4 v0000014374388880_0, 0, 6;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.bit_reverse, S_0000014374382f00;
    %pad/u 32;
    %store/vec4 v0000014374386d00_0, 0, 32;
    %load/vec4 v00000143743873e0_0;
    %load/vec4 v0000014374386d00_0;
    %cmp/s;
    %jmp/0xz  T_3.18, 5;
    %ix/getv/s 4, v00000143743873e0_0;
    %load/vec4a v0000014374386e40, 4;
    %pad/s 32;
    %store/vec4 v0000014374386da0_0, 0, 32;
    %ix/getv/s 4, v00000143743873e0_0;
    %load/vec4a v0000014374387de0, 4;
    %pad/s 32;
    %store/vec4 v0000014374388560_0, 0, 32;
    %ix/getv/s 4, v0000014374386d00_0;
    %load/vec4a v0000014374386e40, 4;
    %ix/getv/s 4, v00000143743873e0_0;
    %store/vec4a v0000014374386e40, 4, 0;
    %ix/getv/s 4, v0000014374386d00_0;
    %load/vec4a v0000014374387de0, 4;
    %ix/getv/s 4, v00000143743873e0_0;
    %store/vec4a v0000014374387de0, 4, 0;
    %load/vec4 v0000014374386da0_0;
    %parti/s 16, 0, 2;
    %ix/getv/s 4, v0000014374386d00_0;
    %store/vec4a v0000014374386e40, 4, 0;
    %load/vec4 v0000014374388560_0;
    %parti/s 16, 0, 2;
    %ix/getv/s 4, v0000014374386d00_0;
    %store/vec4a v0000014374387de0, 4, 0;
T_3.18 ;
    %load/vec4 v00000143743873e0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743873e0_0, 0, 32;
    %jmp T_3.16;
T_3.17 ;
    %pushi/vec4 2, 0, 32;
    %store/vec4 v0000014374387e80_0, 0, 32;
T_3.20 ;
    %load/vec4 v0000014374387e80_0;
    %cmpi/s 64, 0, 32;
    %flag_or 5, 4;
    %jmp/0xz T_3.21, 5;
    %load/vec4 v0000014374387e80_0;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %shiftr 4;
    %store/vec4 v00000143743861c0_0, 0, 32;
    %pushi/vec4 64, 0, 32;
    %load/vec4 v0000014374387e80_0;
    %div/s;
    %store/vec4 v0000014374388380_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743882e0_0, 0, 32;
T_3.22 ;
    %load/vec4 v00000143743882e0_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_3.23, 5;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374386d00_0, 0, 32;
T_3.24 ;
    %load/vec4 v0000014374386d00_0;
    %load/vec4 v00000143743861c0_0;
    %cmp/s;
    %jmp/0xz T_3.25, 5;
    %load/vec4 v0000014374386d00_0;
    %load/vec4 v0000014374388380_0;
    %mul;
    %store/vec4 v0000014374386300_0, 0, 32;
    %load/vec4 v0000014374386300_0;
    %store/vec4 v0000014374386940_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.tw_re, S_0000014374383220;
    %store/vec4 v00000143743863a0_0, 0, 16;
    %load/vec4 v0000014374386300_0;
    %store/vec4 v00000143743872a0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.tw_im, S_0000014374383540;
    %store/vec4 v00000143743870c0_0, 0, 16;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %load/vec4 v00000143743861c0_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374386e40, 4;
    %pad/s 32;
    %load/vec4 v00000143743863a0_0;
    %pad/s 32;
    %mul;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %load/vec4 v00000143743861c0_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374387de0, 4;
    %pad/s 32;
    %load/vec4 v00000143743870c0_0;
    %pad/s 32;
    %mul;
    %sub;
    %pushi/vec4 11, 0, 32;
    %store/vec4 v0000014374386c60_0, 0, 32;
    %store/vec4 v0000014374387a20_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.trunc_shift, S_0000014374382be0;
    %store/vec4 v0000014374386620_0, 0, 32;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %load/vec4 v00000143743861c0_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374386e40, 4;
    %pad/s 32;
    %load/vec4 v00000143743870c0_0;
    %pad/s 32;
    %mul;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %load/vec4 v00000143743861c0_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374387de0, 4;
    %pad/s 32;
    %load/vec4 v00000143743863a0_0;
    %pad/s 32;
    %mul;
    %add;
    %pushi/vec4 11, 0, 32;
    %store/vec4 v0000014374386c60_0, 0, 32;
    %store/vec4 v0000014374387a20_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.trunc_shift, S_0000014374382be0;
    %store/vec4 v0000014374387660_0, 0, 32;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374386e40, 4;
    %pad/s 32;
    %store/vec4 v0000014374386da0_0, 0, 32;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374387de0, 4;
    %pad/s 32;
    %store/vec4 v0000014374388560_0, 0, 32;
    %load/vec4 v0000014374386da0_0;
    %load/vec4 v0000014374386620_0;
    %add;
    %store/vec4 v00000143743866c0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.sat16, S_0000014374382410;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v0000014374386e40, 4, 0;
    %load/vec4 v0000014374388560_0;
    %load/vec4 v0000014374387660_0;
    %add;
    %store/vec4 v00000143743866c0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.sat16, S_0000014374382410;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v0000014374387de0, 4, 0;
    %load/vec4 v0000014374386da0_0;
    %load/vec4 v0000014374386620_0;
    %sub;
    %store/vec4 v00000143743866c0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.sat16, S_0000014374382410;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %load/vec4 v00000143743861c0_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v0000014374386e40, 4, 0;
    %load/vec4 v0000014374388560_0;
    %load/vec4 v0000014374387660_0;
    %sub;
    %store/vec4 v00000143743866c0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft1.sat16, S_0000014374382410;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374386d00_0;
    %add;
    %load/vec4 v00000143743861c0_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v0000014374387de0, 4, 0;
    %load/vec4 v0000014374386d00_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374386d00_0, 0, 32;
    %jmp T_3.24;
T_3.25 ;
    %load/vec4 v00000143743882e0_0;
    %load/vec4 v0000014374387e80_0;
    %add;
    %store/vec4 v00000143743882e0_0, 0, 32;
    %jmp T_3.22;
T_3.23 ;
    %load/vec4 v0000014374387e80_0;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %shiftl 4;
    %store/vec4 v0000014374387e80_0, 0, 32;
    %jmp T_3.20;
T_3.21 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743873e0_0, 0, 32;
T_3.26 ;
    %load/vec4 v00000143743873e0_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_3.27, 5;
    %ix/getv/s 4, v00000143743873e0_0;
    %load/vec4a v0000014374386e40, 4;
    %load/vec4 v0000014374386800_0;
    %load/vec4 v00000143743873e0_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743889c0, 0, 4;
    %ix/getv/s 4, v00000143743873e0_0;
    %load/vec4a v0000014374387de0, 4;
    %load/vec4 v0000014374386800_0;
    %load/vec4 v00000143743873e0_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374389aa0, 0, 4;
    %load/vec4 v00000143743873e0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743873e0_0, 0, 32;
    %jmp T_3.26;
T_3.27 ;
    %end;
S_0000014374382410 .scope function.vec4.u16, "sat16" "sat16" 11 37, 11 37 0, S_0000014374382a50;
 .timescale -9 -12;
; Variable sat16 is vec4 return value of scope S_0000014374382410
v00000143743866c0_0 .var/s "val", 31 0;
TD_tb_top_receiver.u_top.u_fft1.sat16 ;
    %load/vec4 v00000143743866c0_0;
    %cmpi/s 32767, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_4.28, 5;
    %pushi/vec4 32767, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to sat16 (store_vec4_to_lval)
    %jmp T_4.29;
T_4.28 ;
    %load/vec4 v00000143743866c0_0;
    %cmpi/s 4294934528, 0, 32;
    %jmp/0xz  T_4.30, 5;
    %pushi/vec4 32768, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to sat16 (store_vec4_to_lval)
    %jmp T_4.31;
T_4.30 ;
    %load/vec4 v00000143743866c0_0;
    %parti/s 16, 0, 2;
    %ret/vec4 0, 0, 16;  Assign to sat16 (store_vec4_to_lval)
T_4.31 ;
T_4.29 ;
    %end;
S_0000014374382be0 .scope function.vec4.u32, "trunc_shift" "trunc_shift" 11 47, 11 47 0, S_0000014374382a50;
 .timescale -9 -12;
v0000014374386c60_0 .var/i "sh", 31 0;
; Variable trunc_shift is vec4 return value of scope S_0000014374382be0
v0000014374387a20_0 .var/s "val", 31 0;
TD_tb_top_receiver.u_top.u_fft1.trunc_shift ;
    %load/vec4 v0000014374387a20_0;
    %load/vec4 v0000014374386c60_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %ret/vec4 0, 0, 32;  Assign to trunc_shift (store_vec4_to_lval)
    %end;
S_0000014374383540 .scope function.vec4.u16, "tw_im" "tw_im" 11 69, 11 69 0, S_0000014374382a50;
 .timescale -9 -12;
v0000014374387200_0 .var/real "ang", 0 0;
v00000143743872a0_0 .var/i "idx", 31 0;
v0000014374387480_0 .var/real "s", 0 0;
; Variable tw_im is vec4 return value of scope S_0000014374383540
TD_tb_top_receiver.u_top.u_fft1.tw_im ;
    %pushi/real 1686629713, 20452; load=-6.28319
    %pushi/real 273688, 20430; load=-6.28319
    %add/wr;
    %load/vec4 v00000143743872a0_0;
    %cvt/rv/s;
    %mul/wr;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %store/real v0000014374387200_0;
    %vpi_func/r 11 75 "$sin", v0000014374387200_0 {0 0 0};
    %pushi/real 1073741824, 4077; load=2048.00
    %mul/wr;
    %store/real v0000014374387480_0;
    %pushi/real 2147418112, 4080; load=32767.0
    %load/real v0000014374387480_0;
    %cmp/wr;
    %jmp/0xz  T_6.32, 5;
    %pushi/vec4 32767, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_im (store_vec4_to_lval)
    %jmp T_6.33;
T_6.32 ;
    %load/real v0000014374387480_0;
    %pushi/real 1073741824, 20465; load=-32768.0
    %cmp/wr;
    %jmp/0xz  T_6.34, 5;
    %pushi/vec4 32768, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_im (store_vec4_to_lval)
    %jmp T_6.35;
T_6.34 ;
    %vpi_func 11 78 "$rtoi" 32, v0000014374387480_0 {0 0 0};
    %pad/s 16;
    %ret/vec4 0, 0, 16;  Assign to tw_im (store_vec4_to_lval)
T_6.35 ;
T_6.33 ;
    %end;
S_0000014374383220 .scope function.vec4.u16, "tw_re" "tw_re" 11 56, 11 56 0, S_0000014374382a50;
 .timescale -9 -12;
v00000143743868a0_0 .var/real "ang", 0 0;
v0000014374386bc0_0 .var/real "c", 0 0;
v0000014374386940_0 .var/i "idx", 31 0;
; Variable tw_re is vec4 return value of scope S_0000014374383220
TD_tb_top_receiver.u_top.u_fft1.tw_re ;
    %pushi/real 1686629713, 20452; load=-6.28319
    %pushi/real 273688, 20430; load=-6.28319
    %add/wr;
    %load/vec4 v0000014374386940_0;
    %cvt/rv/s;
    %mul/wr;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %store/real v00000143743868a0_0;
    %vpi_func/r 11 62 "$cos", v00000143743868a0_0 {0 0 0};
    %pushi/real 1073741824, 4077; load=2048.00
    %mul/wr;
    %store/real v0000014374386bc0_0;
    %pushi/real 2147418112, 4080; load=32767.0
    %load/real v0000014374386bc0_0;
    %cmp/wr;
    %jmp/0xz  T_7.36, 5;
    %pushi/vec4 32767, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_re (store_vec4_to_lval)
    %jmp T_7.37;
T_7.36 ;
    %load/real v0000014374386bc0_0;
    %pushi/real 1073741824, 20465; load=-32768.0
    %cmp/wr;
    %jmp/0xz  T_7.38, 5;
    %pushi/vec4 32768, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_re (store_vec4_to_lval)
    %jmp T_7.39;
T_7.38 ;
    %vpi_func 11 65 "$rtoi" 32, v0000014374386bc0_0 {0 0 0};
    %pad/s 16;
    %ret/vec4 0, 0, 16;  Assign to tw_re (store_vec4_to_lval)
T_7.39 ;
T_7.37 ;
    %end;
S_0000014374382730 .scope module, "u_fft2" "fft_64pt" 4 269, 11 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "i_start";
    .port_info 3 /OUTPUT 1 "o_done";
    .port_info 4 /INPUT 1 "i_load_valid";
    .port_info 5 /INPUT 16 "i_load_re";
    .port_info 6 /INPUT 16 "i_load_im";
    .port_info 7 /INPUT 6 "i_read_addr";
    .port_info 8 /OUTPUT 16 "o_read_re";
    .port_info 9 /OUTPUT 16 "o_read_im";
L_0000014374303540 .functor BUFZ 16, L_00000143744084c0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_00000143743048f0 .functor BUFZ 16, L_00000143744082e0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
v000001437438aa90_0 .net *"_ivl_0", 15 0, L_00000143744084c0;  1 drivers
v000001437438bcb0_0 .net *"_ivl_10", 15 0, L_00000143744082e0;  1 drivers
v000001437438bdf0_0 .net *"_ivl_12", 6 0, L_00000143744078e0;  1 drivers
v000001437438c6b0_0 .net *"_ivl_14", 8 0, L_0000014374407d40;  1 drivers
L_00000143743a9608 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001437438b710_0 .net *"_ivl_17", 1 0, L_00000143743a9608;  1 drivers
v000001437438aef0_0 .net *"_ivl_2", 6 0, L_0000014374407200;  1 drivers
v000001437438a130_0 .net *"_ivl_4", 8 0, L_00000143744070c0;  1 drivers
L_00000143743a95c0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v000001437438c750_0 .net *"_ivl_7", 1 0, L_00000143743a95c0;  1 drivers
v000001437438b530_0 .var "bank_calc", 0 0;
v000001437438a630_0 .var "bank_in", 0 0;
v000001437438bfd0_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v000001437438bf30_0 .net/s "i_load_im", 15 0, v000001437438db50_0;  alias, 1 drivers
v000001437438ac70_0 .net/s "i_load_re", 15 0, v000001437438d1f0_0;  alias, 1 drivers
v000001437438c070_0 .net "i_load_valid", 0 0, L_0000014374303070;  alias, 1 drivers
v000001437438c390_0 .net "i_read_addr", 5 0, v000001437439a010_0;  alias, 1 drivers
L_00000143743a9650 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v000001437438a590_0 .net "i_start", 0 0, L_00000143743a9650;  1 drivers
v000001437438b5d0_0 .var "input_ready_pulse", 0 0;
v000001437438ad10_0 .var "load_cnt", 6 0;
v000001437438c110 .array/s "mem_im", 127 0, 15 0;
v000001437438ae50 .array/s "mem_re", 127 0, 15 0;
v000001437438a450_0 .var "o_done", 0 0;
v000001437438c7f0_0 .net/s "o_read_im", 15 0, L_00000143743048f0;  alias, 1 drivers
v000001437438af90_0 .net/s "o_read_re", 15 0, L_0000014374303540;  alias, 1 drivers
v000001437438c1b0_0 .var "pending_bank", 0 0;
v000001437438a270_0 .var "pending_valid", 0 0;
v000001437438c2f0_0 .var "read_hold", 6 0;
v000001437438b670_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
L_00000143744084c0 .array/port v000001437438ae50, L_00000143744070c0;
L_0000014374407200 .concat [ 6 1 0 0], v000001437439a010_0, v000001437438b530_0;
L_00000143744070c0 .concat [ 7 2 0 0], L_0000014374407200, L_00000143743a95c0;
L_00000143744082e0 .array/port v000001437438c110, L_0000014374407d40;
L_00000143744078e0 .concat [ 6 1 0 0], v000001437439a010_0, v000001437438b530_0;
L_0000014374407d40 .concat [ 7 2 0 0], L_00000143744078e0, L_00000143743a9608;
S_0000014374383b80 .scope function.vec4.s6, "bit_reverse" "bit_reverse" 11 29, 11 29 0, S_0000014374382730;
 .timescale -9 -12;
; Variable bit_reverse is vec4 return value of scope S_0000014374383b80
v0000014374389140_0 .var "in", 5 0;
TD_tb_top_receiver.u_top.u_fft2.bit_reverse ;
    %load/vec4 v0000014374389140_0;
    %parti/s 1, 0, 2;
    %load/vec4 v0000014374389140_0;
    %parti/s 1, 1, 2;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374389140_0;
    %parti/s 1, 2, 3;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374389140_0;
    %parti/s 1, 3, 3;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374389140_0;
    %parti/s 1, 4, 4;
    %concat/vec4; draw_concat_vec4
    %load/vec4 v0000014374389140_0;
    %parti/s 1, 5, 4;
    %concat/vec4; draw_concat_vec4
    %ret/vec4 0, 0, 6;  Assign to bit_reverse (store_vec4_to_lval)
    %end;
S_00000143743839f0 .scope autotask, "run_fft" "run_fft" 11 110, 11 110 0, S_0000014374382730;
 .timescale -9 -12;
v00000143743891e0 .array/s "buf_im", 63 0, 15 0;
v0000014374389e60 .array/s "buf_re", 63 0, 15 0;
v0000014374388a60_0 .var/i "half", 31 0;
v0000014374388b00_0 .var/i "i", 31 0;
v0000014374388ba0_0 .var/i "idx", 31 0;
v0000014374388ce0_0 .var/i "j", 31 0;
v0000014374388d80_0 .var/i "k", 31 0;
v0000014374389640_0 .var/i "m", 31 0;
v0000014374388e20_0 .var/i "step", 31 0;
v0000014374389280_0 .var/s "t_im", 31 0;
v00000143743893c0_0 .var/s "t_re", 31 0;
v0000014374389460_0 .var/s "u_im", 31 0;
v0000014374389500_0 .var/s "u_re", 31 0;
v00000143743895a0_0 .var/s "w_im", 15 0;
v000001437438b030_0 .var/s "w_re", 15 0;
v000001437438ab30_0 .var "which_bank", 0 0;
TD_tb_top_receiver.u_top.u_fft2.run_fft ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374388b00_0, 0, 32;
T_9.40 ;
    %load/vec4 v0000014374388b00_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_9.41, 5;
    %load/vec4 v000001437438ab30_0;
    %load/vec4 v0000014374388b00_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v000001437438ae50, 4;
    %ix/getv/s 4, v0000014374388b00_0;
    %store/vec4a v0000014374389e60, 4, 0;
    %load/vec4 v000001437438ab30_0;
    %load/vec4 v0000014374388b00_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v000001437438c110, 4;
    %ix/getv/s 4, v0000014374388b00_0;
    %store/vec4a v00000143743891e0, 4, 0;
    %load/vec4 v0000014374388b00_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374388b00_0, 0, 32;
    %jmp T_9.40;
T_9.41 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374388b00_0, 0, 32;
T_9.42 ;
    %load/vec4 v0000014374388b00_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_9.43, 5;
    %load/vec4 v0000014374388b00_0;
    %parti/s 6, 0, 2;
    %store/vec4 v0000014374389140_0, 0, 6;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.bit_reverse, S_0000014374383b80;
    %pad/u 32;
    %store/vec4 v0000014374388ce0_0, 0, 32;
    %load/vec4 v0000014374388b00_0;
    %load/vec4 v0000014374388ce0_0;
    %cmp/s;
    %jmp/0xz  T_9.44, 5;
    %ix/getv/s 4, v0000014374388b00_0;
    %load/vec4a v0000014374389e60, 4;
    %pad/s 32;
    %store/vec4 v0000014374389500_0, 0, 32;
    %ix/getv/s 4, v0000014374388b00_0;
    %load/vec4a v00000143743891e0, 4;
    %pad/s 32;
    %store/vec4 v0000014374389460_0, 0, 32;
    %ix/getv/s 4, v0000014374388ce0_0;
    %load/vec4a v0000014374389e60, 4;
    %ix/getv/s 4, v0000014374388b00_0;
    %store/vec4a v0000014374389e60, 4, 0;
    %ix/getv/s 4, v0000014374388ce0_0;
    %load/vec4a v00000143743891e0, 4;
    %ix/getv/s 4, v0000014374388b00_0;
    %store/vec4a v00000143743891e0, 4, 0;
    %load/vec4 v0000014374389500_0;
    %parti/s 16, 0, 2;
    %ix/getv/s 4, v0000014374388ce0_0;
    %store/vec4a v0000014374389e60, 4, 0;
    %load/vec4 v0000014374389460_0;
    %parti/s 16, 0, 2;
    %ix/getv/s 4, v0000014374388ce0_0;
    %store/vec4a v00000143743891e0, 4, 0;
T_9.44 ;
    %load/vec4 v0000014374388b00_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374388b00_0, 0, 32;
    %jmp T_9.42;
T_9.43 ;
    %pushi/vec4 2, 0, 32;
    %store/vec4 v0000014374389640_0, 0, 32;
T_9.46 ;
    %load/vec4 v0000014374389640_0;
    %cmpi/s 64, 0, 32;
    %flag_or 5, 4;
    %jmp/0xz T_9.47, 5;
    %load/vec4 v0000014374389640_0;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %shiftr 4;
    %store/vec4 v0000014374388a60_0, 0, 32;
    %pushi/vec4 64, 0, 32;
    %load/vec4 v0000014374389640_0;
    %div/s;
    %store/vec4 v0000014374388e20_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374388d80_0, 0, 32;
T_9.48 ;
    %load/vec4 v0000014374388d80_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_9.49, 5;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374388ce0_0, 0, 32;
T_9.50 ;
    %load/vec4 v0000014374388ce0_0;
    %load/vec4 v0000014374388a60_0;
    %cmp/s;
    %jmp/0xz T_9.51, 5;
    %load/vec4 v0000014374388ce0_0;
    %load/vec4 v0000014374388e20_0;
    %mul;
    %store/vec4 v0000014374388ba0_0, 0, 32;
    %load/vec4 v0000014374388ba0_0;
    %store/vec4 v000001437438c430_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.tw_re, S_00000143743825a0;
    %store/vec4 v000001437438b030_0, 0, 16;
    %load/vec4 v0000014374388ba0_0;
    %store/vec4 v000001437438adb0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.tw_im, S_0000014374383ea0;
    %store/vec4 v00000143743895a0_0, 0, 16;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %load/vec4 v0000014374388a60_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374389e60, 4;
    %pad/s 32;
    %load/vec4 v000001437438b030_0;
    %pad/s 32;
    %mul;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %load/vec4 v0000014374388a60_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v00000143743891e0, 4;
    %pad/s 32;
    %load/vec4 v00000143743895a0_0;
    %pad/s 32;
    %mul;
    %sub;
    %pushi/vec4 11, 0, 32;
    %store/vec4 v000001437438be90_0, 0, 32;
    %store/vec4 v000001437438b3f0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.trunc_shift, S_00000143743833b0;
    %store/vec4 v00000143743893c0_0, 0, 32;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %load/vec4 v0000014374388a60_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374389e60, 4;
    %pad/s 32;
    %load/vec4 v00000143743895a0_0;
    %pad/s 32;
    %mul;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %load/vec4 v0000014374388a60_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v00000143743891e0, 4;
    %pad/s 32;
    %load/vec4 v000001437438b030_0;
    %pad/s 32;
    %mul;
    %add;
    %pushi/vec4 11, 0, 32;
    %store/vec4 v000001437438be90_0, 0, 32;
    %store/vec4 v000001437438b3f0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.trunc_shift, S_00000143743833b0;
    %store/vec4 v0000014374389280_0, 0, 32;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v0000014374389e60, 4;
    %pad/s 32;
    %store/vec4 v0000014374389500_0, 0, 32;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %ix/vec4/s 4;
    %load/vec4a v00000143743891e0, 4;
    %pad/s 32;
    %store/vec4 v0000014374389460_0, 0, 32;
    %load/vec4 v0000014374389500_0;
    %load/vec4 v00000143743893c0_0;
    %add;
    %store/vec4 v000001437438a9f0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.sat16, S_0000014374382280;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v0000014374389e60, 4, 0;
    %load/vec4 v0000014374389460_0;
    %load/vec4 v0000014374389280_0;
    %add;
    %store/vec4 v000001437438a9f0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.sat16, S_0000014374382280;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v00000143743891e0, 4, 0;
    %load/vec4 v0000014374389500_0;
    %load/vec4 v00000143743893c0_0;
    %sub;
    %store/vec4 v000001437438a9f0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.sat16, S_0000014374382280;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %load/vec4 v0000014374388a60_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v0000014374389e60, 4, 0;
    %load/vec4 v0000014374389460_0;
    %load/vec4 v0000014374389280_0;
    %sub;
    %store/vec4 v000001437438a9f0_0, 0, 32;
    %callf/vec4 TD_tb_top_receiver.u_top.u_fft2.sat16, S_0000014374382280;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374388ce0_0;
    %add;
    %load/vec4 v0000014374388a60_0;
    %add;
    %ix/vec4/s 4;
    %store/vec4a v00000143743891e0, 4, 0;
    %load/vec4 v0000014374388ce0_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374388ce0_0, 0, 32;
    %jmp T_9.50;
T_9.51 ;
    %load/vec4 v0000014374388d80_0;
    %load/vec4 v0000014374389640_0;
    %add;
    %store/vec4 v0000014374388d80_0, 0, 32;
    %jmp T_9.48;
T_9.49 ;
    %load/vec4 v0000014374389640_0;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %shiftl 4;
    %store/vec4 v0000014374389640_0, 0, 32;
    %jmp T_9.46;
T_9.47 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374388b00_0, 0, 32;
T_9.52 ;
    %load/vec4 v0000014374388b00_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_9.53, 5;
    %ix/getv/s 4, v0000014374388b00_0;
    %load/vec4a v0000014374389e60, 4;
    %load/vec4 v000001437438ab30_0;
    %load/vec4 v0000014374388b00_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437438ae50, 0, 4;
    %ix/getv/s 4, v0000014374388b00_0;
    %load/vec4a v00000143743891e0, 4;
    %load/vec4 v000001437438ab30_0;
    %load/vec4 v0000014374388b00_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437438c110, 0, 4;
    %load/vec4 v0000014374388b00_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374388b00_0, 0, 32;
    %jmp T_9.52;
T_9.53 ;
    %end;
S_0000014374382280 .scope function.vec4.u16, "sat16" "sat16" 11 37, 11 37 0, S_0000014374382730;
 .timescale -9 -12;
; Variable sat16 is vec4 return value of scope S_0000014374382280
v000001437438a9f0_0 .var/s "val", 31 0;
TD_tb_top_receiver.u_top.u_fft2.sat16 ;
    %load/vec4 v000001437438a9f0_0;
    %cmpi/s 32767, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_10.54, 5;
    %pushi/vec4 32767, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to sat16 (store_vec4_to_lval)
    %jmp T_10.55;
T_10.54 ;
    %load/vec4 v000001437438a9f0_0;
    %cmpi/s 4294934528, 0, 32;
    %jmp/0xz  T_10.56, 5;
    %pushi/vec4 32768, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to sat16 (store_vec4_to_lval)
    %jmp T_10.57;
T_10.56 ;
    %load/vec4 v000001437438a9f0_0;
    %parti/s 16, 0, 2;
    %ret/vec4 0, 0, 16;  Assign to sat16 (store_vec4_to_lval)
T_10.57 ;
T_10.55 ;
    %end;
S_00000143743833b0 .scope function.vec4.u32, "trunc_shift" "trunc_shift" 11 47, 11 47 0, S_0000014374382730;
 .timescale -9 -12;
v000001437438be90_0 .var/i "sh", 31 0;
; Variable trunc_shift is vec4 return value of scope S_00000143743833b0
v000001437438b3f0_0 .var/s "val", 31 0;
TD_tb_top_receiver.u_top.u_fft2.trunc_shift ;
    %load/vec4 v000001437438b3f0_0;
    %load/vec4 v000001437438be90_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %ret/vec4 0, 0, 32;  Assign to trunc_shift (store_vec4_to_lval)
    %end;
S_0000014374383ea0 .scope function.vec4.u16, "tw_im" "tw_im" 11 69, 11 69 0, S_0000014374382730;
 .timescale -9 -12;
v000001437438abd0_0 .var/real "ang", 0 0;
v000001437438adb0_0 .var/i "idx", 31 0;
v000001437438b210_0 .var/real "s", 0 0;
; Variable tw_im is vec4 return value of scope S_0000014374383ea0
TD_tb_top_receiver.u_top.u_fft2.tw_im ;
    %pushi/real 1686629713, 20452; load=-6.28319
    %pushi/real 273688, 20430; load=-6.28319
    %add/wr;
    %load/vec4 v000001437438adb0_0;
    %cvt/rv/s;
    %mul/wr;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %store/real v000001437438abd0_0;
    %vpi_func/r 11 75 "$sin", v000001437438abd0_0 {0 0 0};
    %pushi/real 1073741824, 4077; load=2048.00
    %mul/wr;
    %store/real v000001437438b210_0;
    %pushi/real 2147418112, 4080; load=32767.0
    %load/real v000001437438b210_0;
    %cmp/wr;
    %jmp/0xz  T_12.58, 5;
    %pushi/vec4 32767, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_im (store_vec4_to_lval)
    %jmp T_12.59;
T_12.58 ;
    %load/real v000001437438b210_0;
    %pushi/real 1073741824, 20465; load=-32768.0
    %cmp/wr;
    %jmp/0xz  T_12.60, 5;
    %pushi/vec4 32768, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_im (store_vec4_to_lval)
    %jmp T_12.61;
T_12.60 ;
    %vpi_func 11 78 "$rtoi" 32, v000001437438b210_0 {0 0 0};
    %pad/s 16;
    %ret/vec4 0, 0, 16;  Assign to tw_im (store_vec4_to_lval)
T_12.61 ;
T_12.59 ;
    %end;
S_00000143743825a0 .scope function.vec4.u16, "tw_re" "tw_re" 11 56, 11 56 0, S_0000014374382730;
 .timescale -9 -12;
v000001437438b350_0 .var/real "ang", 0 0;
v000001437438b490_0 .var/real "c", 0 0;
v000001437438c430_0 .var/i "idx", 31 0;
; Variable tw_re is vec4 return value of scope S_00000143743825a0
TD_tb_top_receiver.u_top.u_fft2.tw_re ;
    %pushi/real 1686629713, 20452; load=-6.28319
    %pushi/real 273688, 20430; load=-6.28319
    %add/wr;
    %load/vec4 v000001437438c430_0;
    %cvt/rv/s;
    %mul/wr;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %store/real v000001437438b350_0;
    %vpi_func/r 11 62 "$cos", v000001437438b350_0 {0 0 0};
    %pushi/real 1073741824, 4077; load=2048.00
    %mul/wr;
    %store/real v000001437438b490_0;
    %pushi/real 2147418112, 4080; load=32767.0
    %load/real v000001437438b490_0;
    %cmp/wr;
    %jmp/0xz  T_13.62, 5;
    %pushi/vec4 32767, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_re (store_vec4_to_lval)
    %jmp T_13.63;
T_13.62 ;
    %load/real v000001437438b490_0;
    %pushi/real 1073741824, 20465; load=-32768.0
    %cmp/wr;
    %jmp/0xz  T_13.64, 5;
    %pushi/vec4 32768, 0, 16;
    %ret/vec4 0, 0, 16;  Assign to tw_re (store_vec4_to_lval)
    %jmp T_13.65;
T_13.64 ;
    %vpi_func 11 65 "$rtoi" 32, v000001437438b490_0 {0 0 0};
    %pad/s 16;
    %ret/vec4 0, 0, 16;  Assign to tw_re (store_vec4_to_lval)
T_13.65 ;
T_13.63 ;
    %end;
S_00000143743820f0 .scope module, "u_nco_ctrl" "nco_phase_ctrl" 4 184, 12 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "cfo_valid";
    .port_info 3 /INPUT 16 "cfo_eps_hat";
    .port_info 4 /INPUT 1 "phase_update_en";
    .port_info 5 /INPUT 1 "phase_err_valid";
    .port_info 6 /INPUT 16 "phase_err";
    .port_info 7 /OUTPUT 16 "phase_out";
    .port_info 8 /OUTPUT 16 "acc_tap";
P_0000014374196a90 .param/l "PHASE_W" 0 12 2, +C4<00000000000000000000000000010000>;
P_0000014374196ac8 .param/l "PI_NEG" 1 12 67, +C4<1110011011011110>;
P_0000014374196b00 .param/l "PI_POS" 1 12 66, +C4<0001100100100010>;
P_0000014374196b38 .param/l "TWO_PI" 1 12 68, +C4<0011001001000100>;
L_0000014374303fc0 .functor BUFZ 16, v000001437438a810_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
v000001437438a810_0 .var/s "acc", 15 0;
v000001437438c570_0 .net/s "acc_tap", 15 0, L_0000014374303fc0;  alias, 1 drivers
v000001437438b170_0 .net/s "cfo_eps_hat", 15 0, v00000143743451e0_0;  alias, 1 drivers
v000001437438a310_0 .net "cfo_valid", 0 0, v0000014374345460_0;  alias, 1 drivers
v000001437438c610_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v000001437438b7b0_0 .var/s "next_acc", 16 0;
v000001437438b0d0_0 .net/s "phase_err", 15 0, v00000143743856e0_0;  alias, 1 drivers
v000001437438ba30_0 .net "phase_err_valid", 0 0, v0000014374384740_0;  alias, 1 drivers
v000001437438b850_0 .var/s "phase_inc", 15 0;
v000001437438bb70_0 .var/s "phase_out", 15 0;
v000001437438a8b0_0 .net "phase_update_en", 0 0, v00000143743991b0_0;  1 drivers
v000001437438b8f0_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
S_000001437438ef40 .scope module, "u_rot" "cfo_rotator" 4 202, 13 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "in_valid";
    .port_info 3 /INPUT 16 "in1_re";
    .port_info 4 /INPUT 16 "in1_im";
    .port_info 5 /INPUT 16 "in2_re";
    .port_info 6 /INPUT 16 "in2_im";
    .port_info 7 /INPUT 16 "phase";
    .port_info 8 /OUTPUT 1 "out_valid";
    .port_info 9 /OUTPUT 16 "out1_re";
    .port_info 10 /OUTPUT 16 "out1_im";
    .port_info 11 /OUTPUT 16 "out2_re";
    .port_info 12 /OUTPUT 16 "out2_im";
P_0000014373d4ac50 .param/l "DATA_W" 0 13 2, +C4<00000000000000000000000000010000>;
P_0000014373d4ac88 .param/l "PHASE_W" 0 13 3, +C4<00000000000000000000000000010000>;
v000001437438d3d0_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v000001437438cd90_0 .net/s "in1_im", 15 0, v0000014374398d50_0;  1 drivers
v000001437438ddd0_0 .net/s "in1_re", 15 0, v0000014374399d90_0;  1 drivers
v000001437438ce30_0 .net/s "in2_im", 15 0, v00000143743992f0_0;  1 drivers
v000001437438cf70_0 .net/s "in2_re", 15 0, v000001437439a1f0_0;  1 drivers
v000001437438dab0_0 .net "in_valid", 0 0, v00000143743991b0_0;  alias, 1 drivers
v000001437438d150_0 .var/s "out1_im", 15 0;
v000001437438dd30_0 .var/s "out1_re", 15 0;
v000001437438db50_0 .var/s "out2_im", 15 0;
v000001437438d1f0_0 .var/s "out2_re", 15 0;
v0000014374390970_0 .var "out_valid", 0 0;
v0000014374391050_0 .net/s "phase", 15 0, L_0000014374304570;  alias, 1 drivers
v00000143743910f0_0 .net/s "rot1_im", 15 0, v000001437438d650_0;  1 drivers
v0000014374390fb0_0 .net/s "rot1_re", 15 0, v000001437438dfb0_0;  1 drivers
v0000014374392630_0 .net/s "rot2_im", 15 0, v000001437438cc50_0;  1 drivers
v0000014374392450_0 .net/s "rot2_re", 15 0, v000001437438dc90_0;  1 drivers
v0000014374390470_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
S_000001437438fa30 .scope module, "u_rot1" "cordic_rotator" 13 24, 9 1 0, S_000001437438ef40;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 16 "x_in";
    .port_info 3 /INPUT 16 "y_in";
    .port_info 4 /INPUT 16 "theta_in";
    .port_info 5 /OUTPUT 16 "x_out";
    .port_info 6 /OUTPUT 16 "y_out";
P_00000143742d7350 .param/l "WIDTH" 0 9 2, +C4<00000000000000000000000000010000>;
v000001437438a1d0_0 .net/s *"_ivl_37", 31 0, L_00000143744081a0;  1 drivers
L_00000143743a8f48 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v000001437438a770_0 .net/2s *"_ivl_39", 31 0, L_00000143743a8f48;  1 drivers
v000001437438b990_0 .net/s *"_ivl_44", 31 0, L_0000014374407c00;  1 drivers
L_00000143743a8f90 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v000001437438a3b0_0 .net/2s *"_ivl_46", 31 0, L_00000143743a8f90;  1 drivers
L_00000143743a8be8 .functor BUFT 1, C4<0000011001001000>, C4<0>, C4<0>, C4<0>;
v000001437438bad0 .array "atan_table", 11 0;
v000001437438bad0_0 .net/s v000001437438bad0 0, 15 0, L_00000143743a8be8; 1 drivers
L_00000143743a8c30 .functor BUFT 1, C4<0000001110110101>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_1 .net/s v000001437438bad0 1, 15 0, L_00000143743a8c30; 1 drivers
L_00000143743a8c78 .functor BUFT 1, C4<0000000111110101>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_2 .net/s v000001437438bad0 2, 15 0, L_00000143743a8c78; 1 drivers
L_00000143743a8cc0 .functor BUFT 1, C4<0000000011111110>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_3 .net/s v000001437438bad0 3, 15 0, L_00000143743a8cc0; 1 drivers
L_00000143743a8d08 .functor BUFT 1, C4<0000000001111111>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_4 .net/s v000001437438bad0 4, 15 0, L_00000143743a8d08; 1 drivers
L_00000143743a8d50 .functor BUFT 1, C4<0000000000111111>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_5 .net/s v000001437438bad0 5, 15 0, L_00000143743a8d50; 1 drivers
L_00000143743a8d98 .functor BUFT 1, C4<0000000000011111>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_6 .net/s v000001437438bad0 6, 15 0, L_00000143743a8d98; 1 drivers
L_00000143743a8de0 .functor BUFT 1, C4<0000000000001111>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_7 .net/s v000001437438bad0 7, 15 0, L_00000143743a8de0; 1 drivers
L_00000143743a8e28 .functor BUFT 1, C4<0000000000000111>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_8 .net/s v000001437438bad0 8, 15 0, L_00000143743a8e28; 1 drivers
L_00000143743a8e70 .functor BUFT 1, C4<0000000000000011>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_9 .net/s v000001437438bad0 9, 15 0, L_00000143743a8e70; 1 drivers
L_00000143743a8eb8 .functor BUFT 1, C4<0000000000000001>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_10 .net/s v000001437438bad0 10, 15 0, L_00000143743a8eb8; 1 drivers
L_00000143743a8f00 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v000001437438bad0_11 .net/s v000001437438bad0 11, 15 0, L_00000143743a8f00; 1 drivers
o0000014374357888 .functor BUFZ 1, C4<z>; HiZ drive
v000001437438a4f0_0 .net "clk", 0 0, o0000014374357888;  0 drivers
v000001437438a6d0_0 .var/i "i", 31 0;
o00000143743578e8 .functor BUFZ 1, C4<z>; HiZ drive
v000001437438a950_0 .net "rst_n", 0 0, o00000143743578e8;  0 drivers
v000001437438bc10_0 .net/s "theta_in", 15 0, L_0000014374304570;  alias, 1 drivers
v000001437438df10 .array/s "x", 12 0, 15 0;
v000001437438de70_0 .net/s "x_in", 15 0, v0000014374399d90_0;  alias, 1 drivers
v000001437438dfb0_0 .var/s "x_out", 15 0;
v000001437438d8d0_0 .net/s "x_scaled", 31 0, L_0000014374406f80;  1 drivers
v000001437438d010 .array/s "y", 12 0, 15 0;
v000001437438d5b0_0 .net/s "y_in", 15 0, v0000014374398d50_0;  alias, 1 drivers
v000001437438d650_0 .var/s "y_out", 15 0;
v000001437438d290_0 .net/s "y_scaled", 31 0, L_0000014374406a80;  1 drivers
v000001437438c930 .array/s "z", 12 0, 15 0;
E_00000143742d7550 .event anyedge, v000001437438d8d0_0, v000001437438d290_0;
v000001437438c930_0 .array/port v000001437438c930, 0;
E_00000143742d7590/0 .event anyedge, v000001437438de70_0, v000001437438d5b0_0, v000001437438bc10_0, v000001437438c930_0;
v000001437438c930_1 .array/port v000001437438c930, 1;
v000001437438c930_2 .array/port v000001437438c930, 2;
v000001437438c930_3 .array/port v000001437438c930, 3;
v000001437438c930_4 .array/port v000001437438c930, 4;
E_00000143742d7590/1 .event anyedge, v000001437438c930_1, v000001437438c930_2, v000001437438c930_3, v000001437438c930_4;
v000001437438c930_5 .array/port v000001437438c930, 5;
v000001437438c930_6 .array/port v000001437438c930, 6;
v000001437438c930_7 .array/port v000001437438c930, 7;
v000001437438c930_8 .array/port v000001437438c930, 8;
E_00000143742d7590/2 .event anyedge, v000001437438c930_5, v000001437438c930_6, v000001437438c930_7, v000001437438c930_8;
v000001437438c930_9 .array/port v000001437438c930, 9;
v000001437438c930_10 .array/port v000001437438c930, 10;
v000001437438c930_11 .array/port v000001437438c930, 11;
v000001437438c930_12 .array/port v000001437438c930, 12;
E_00000143742d7590/3 .event anyedge, v000001437438c930_9, v000001437438c930_10, v000001437438c930_11, v000001437438c930_12;
v000001437438df10_0 .array/port v000001437438df10, 0;
v000001437438df10_1 .array/port v000001437438df10, 1;
v000001437438df10_2 .array/port v000001437438df10, 2;
v000001437438df10_3 .array/port v000001437438df10, 3;
E_00000143742d7590/4 .event anyedge, v000001437438df10_0, v000001437438df10_1, v000001437438df10_2, v000001437438df10_3;
v000001437438df10_4 .array/port v000001437438df10, 4;
v000001437438df10_5 .array/port v000001437438df10, 5;
v000001437438df10_6 .array/port v000001437438df10, 6;
v000001437438df10_7 .array/port v000001437438df10, 7;
E_00000143742d7590/5 .event anyedge, v000001437438df10_4, v000001437438df10_5, v000001437438df10_6, v000001437438df10_7;
v000001437438df10_8 .array/port v000001437438df10, 8;
v000001437438df10_9 .array/port v000001437438df10, 9;
v000001437438df10_10 .array/port v000001437438df10, 10;
v000001437438df10_11 .array/port v000001437438df10, 11;
E_00000143742d7590/6 .event anyedge, v000001437438df10_8, v000001437438df10_9, v000001437438df10_10, v000001437438df10_11;
v000001437438df10_12 .array/port v000001437438df10, 12;
v000001437438d010_0 .array/port v000001437438d010, 0;
v000001437438d010_1 .array/port v000001437438d010, 1;
v000001437438d010_2 .array/port v000001437438d010, 2;
E_00000143742d7590/7 .event anyedge, v000001437438df10_12, v000001437438d010_0, v000001437438d010_1, v000001437438d010_2;
v000001437438d010_3 .array/port v000001437438d010, 3;
v000001437438d010_4 .array/port v000001437438d010, 4;
v000001437438d010_5 .array/port v000001437438d010, 5;
v000001437438d010_6 .array/port v000001437438d010, 6;
E_00000143742d7590/8 .event anyedge, v000001437438d010_3, v000001437438d010_4, v000001437438d010_5, v000001437438d010_6;
v000001437438d010_7 .array/port v000001437438d010, 7;
v000001437438d010_8 .array/port v000001437438d010, 8;
v000001437438d010_9 .array/port v000001437438d010, 9;
v000001437438d010_10 .array/port v000001437438d010, 10;
E_00000143742d7590/9 .event anyedge, v000001437438d010_7, v000001437438d010_8, v000001437438d010_9, v000001437438d010_10;
v000001437438d010_11 .array/port v000001437438d010, 11;
v000001437438d010_12 .array/port v000001437438d010, 12;
E_00000143742d7590/10 .event anyedge, v000001437438d010_11, v000001437438d010_12, v000001437438bad0_0, v000001437438bad0_1;
E_00000143742d7590/11 .event anyedge, v000001437438bad0_2, v000001437438bad0_3, v000001437438bad0_4, v000001437438bad0_5;
E_00000143742d7590/12 .event anyedge, v000001437438bad0_6, v000001437438bad0_7, v000001437438bad0_8, v000001437438bad0_9;
E_00000143742d7590/13 .event anyedge, v000001437438bad0_10, v000001437438bad0_11;
E_00000143742d7590 .event/or E_00000143742d7590/0, E_00000143742d7590/1, E_00000143742d7590/2, E_00000143742d7590/3, E_00000143742d7590/4, E_00000143742d7590/5, E_00000143742d7590/6, E_00000143742d7590/7, E_00000143742d7590/8, E_00000143742d7590/9, E_00000143742d7590/10, E_00000143742d7590/11, E_00000143742d7590/12, E_00000143742d7590/13;
L_00000143744081a0 .extend/s 32, v000001437438df10_12;
L_0000014374406f80 .arith/mult 32, L_00000143744081a0, L_00000143743a8f48;
L_0000014374407c00 .extend/s 32, v000001437438d010_12;
L_0000014374406a80 .arith/mult 32, L_0000014374407c00, L_00000143743a8f90;
S_000001437438ea90 .scope module, "u_rot2" "cordic_rotator" 13 29, 9 1 0, S_000001437438ef40;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 16 "x_in";
    .port_info 3 /INPUT 16 "y_in";
    .port_info 4 /INPUT 16 "theta_in";
    .port_info 5 /OUTPUT 16 "x_out";
    .port_info 6 /OUTPUT 16 "y_out";
P_00000143742d7410 .param/l "WIDTH" 0 9 2, +C4<00000000000000000000000000010000>;
v000001437438ced0_0 .net/s *"_ivl_37", 31 0, L_0000014374406940;  1 drivers
L_00000143743a9338 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v000001437438d970_0 .net/2s *"_ivl_39", 31 0, L_00000143743a9338;  1 drivers
v000001437438da10_0 .net/s *"_ivl_44", 31 0, L_00000143744077a0;  1 drivers
L_00000143743a9380 .functor BUFT 1, C4<00000000000000000000010011011011>, C4<0>, C4<0>, C4<0>;
v000001437438c9d0_0 .net/2s *"_ivl_46", 31 0, L_00000143743a9380;  1 drivers
L_00000143743a8fd8 .functor BUFT 1, C4<0000011001001000>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0 .array "atan_table", 11 0;
v000001437438d6f0_0 .net/s v000001437438d6f0 0, 15 0, L_00000143743a8fd8; 1 drivers
L_00000143743a9020 .functor BUFT 1, C4<0000001110110101>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_1 .net/s v000001437438d6f0 1, 15 0, L_00000143743a9020; 1 drivers
L_00000143743a9068 .functor BUFT 1, C4<0000000111110101>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_2 .net/s v000001437438d6f0 2, 15 0, L_00000143743a9068; 1 drivers
L_00000143743a90b0 .functor BUFT 1, C4<0000000011111110>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_3 .net/s v000001437438d6f0 3, 15 0, L_00000143743a90b0; 1 drivers
L_00000143743a90f8 .functor BUFT 1, C4<0000000001111111>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_4 .net/s v000001437438d6f0 4, 15 0, L_00000143743a90f8; 1 drivers
L_00000143743a9140 .functor BUFT 1, C4<0000000000111111>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_5 .net/s v000001437438d6f0 5, 15 0, L_00000143743a9140; 1 drivers
L_00000143743a9188 .functor BUFT 1, C4<0000000000011111>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_6 .net/s v000001437438d6f0 6, 15 0, L_00000143743a9188; 1 drivers
L_00000143743a91d0 .functor BUFT 1, C4<0000000000001111>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_7 .net/s v000001437438d6f0 7, 15 0, L_00000143743a91d0; 1 drivers
L_00000143743a9218 .functor BUFT 1, C4<0000000000000111>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_8 .net/s v000001437438d6f0 8, 15 0, L_00000143743a9218; 1 drivers
L_00000143743a9260 .functor BUFT 1, C4<0000000000000011>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_9 .net/s v000001437438d6f0 9, 15 0, L_00000143743a9260; 1 drivers
L_00000143743a92a8 .functor BUFT 1, C4<0000000000000001>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_10 .net/s v000001437438d6f0 10, 15 0, L_00000143743a92a8; 1 drivers
L_00000143743a92f0 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>;
v000001437438d6f0_11 .net/s v000001437438d6f0 11, 15 0, L_00000143743a92f0; 1 drivers
o0000014374358608 .functor BUFZ 1, C4<z>; HiZ drive
v000001437438ccf0_0 .net "clk", 0 0, o0000014374358608;  0 drivers
v000001437438dbf0_0 .var/i "i", 31 0;
o0000014374358668 .functor BUFZ 1, C4<z>; HiZ drive
v000001437438d790_0 .net "rst_n", 0 0, o0000014374358668;  0 drivers
v000001437438d0b0_0 .net/s "theta_in", 15 0, L_0000014374304570;  alias, 1 drivers
v000001437438d830 .array/s "x", 12 0, 15 0;
v000001437438cbb0_0 .net/s "x_in", 15 0, v000001437439a1f0_0;  alias, 1 drivers
v000001437438dc90_0 .var/s "x_out", 15 0;
v000001437438d510_0 .net/s "x_scaled", 31 0, L_0000014374407ac0;  1 drivers
v000001437438ca70 .array/s "y", 12 0, 15 0;
v000001437438cb10_0 .net/s "y_in", 15 0, v00000143743992f0_0;  alias, 1 drivers
v000001437438cc50_0 .var/s "y_out", 15 0;
v000001437438d330_0 .net/s "y_scaled", 31 0, L_0000014374408240;  1 drivers
v000001437438d470 .array/s "z", 12 0, 15 0;
E_00000143742d6fd0 .event anyedge, v000001437438d510_0, v000001437438d330_0;
v000001437438d470_0 .array/port v000001437438d470, 0;
E_00000143742d7610/0 .event anyedge, v000001437438cbb0_0, v000001437438cb10_0, v000001437438bc10_0, v000001437438d470_0;
v000001437438d470_1 .array/port v000001437438d470, 1;
v000001437438d470_2 .array/port v000001437438d470, 2;
v000001437438d470_3 .array/port v000001437438d470, 3;
v000001437438d470_4 .array/port v000001437438d470, 4;
E_00000143742d7610/1 .event anyedge, v000001437438d470_1, v000001437438d470_2, v000001437438d470_3, v000001437438d470_4;
v000001437438d470_5 .array/port v000001437438d470, 5;
v000001437438d470_6 .array/port v000001437438d470, 6;
v000001437438d470_7 .array/port v000001437438d470, 7;
v000001437438d470_8 .array/port v000001437438d470, 8;
E_00000143742d7610/2 .event anyedge, v000001437438d470_5, v000001437438d470_6, v000001437438d470_7, v000001437438d470_8;
v000001437438d470_9 .array/port v000001437438d470, 9;
v000001437438d470_10 .array/port v000001437438d470, 10;
v000001437438d470_11 .array/port v000001437438d470, 11;
v000001437438d470_12 .array/port v000001437438d470, 12;
E_00000143742d7610/3 .event anyedge, v000001437438d470_9, v000001437438d470_10, v000001437438d470_11, v000001437438d470_12;
v000001437438d830_0 .array/port v000001437438d830, 0;
v000001437438d830_1 .array/port v000001437438d830, 1;
v000001437438d830_2 .array/port v000001437438d830, 2;
v000001437438d830_3 .array/port v000001437438d830, 3;
E_00000143742d7610/4 .event anyedge, v000001437438d830_0, v000001437438d830_1, v000001437438d830_2, v000001437438d830_3;
v000001437438d830_4 .array/port v000001437438d830, 4;
v000001437438d830_5 .array/port v000001437438d830, 5;
v000001437438d830_6 .array/port v000001437438d830, 6;
v000001437438d830_7 .array/port v000001437438d830, 7;
E_00000143742d7610/5 .event anyedge, v000001437438d830_4, v000001437438d830_5, v000001437438d830_6, v000001437438d830_7;
v000001437438d830_8 .array/port v000001437438d830, 8;
v000001437438d830_9 .array/port v000001437438d830, 9;
v000001437438d830_10 .array/port v000001437438d830, 10;
v000001437438d830_11 .array/port v000001437438d830, 11;
E_00000143742d7610/6 .event anyedge, v000001437438d830_8, v000001437438d830_9, v000001437438d830_10, v000001437438d830_11;
v000001437438d830_12 .array/port v000001437438d830, 12;
v000001437438ca70_0 .array/port v000001437438ca70, 0;
v000001437438ca70_1 .array/port v000001437438ca70, 1;
v000001437438ca70_2 .array/port v000001437438ca70, 2;
E_00000143742d7610/7 .event anyedge, v000001437438d830_12, v000001437438ca70_0, v000001437438ca70_1, v000001437438ca70_2;
v000001437438ca70_3 .array/port v000001437438ca70, 3;
v000001437438ca70_4 .array/port v000001437438ca70, 4;
v000001437438ca70_5 .array/port v000001437438ca70, 5;
v000001437438ca70_6 .array/port v000001437438ca70, 6;
E_00000143742d7610/8 .event anyedge, v000001437438ca70_3, v000001437438ca70_4, v000001437438ca70_5, v000001437438ca70_6;
v000001437438ca70_7 .array/port v000001437438ca70, 7;
v000001437438ca70_8 .array/port v000001437438ca70, 8;
v000001437438ca70_9 .array/port v000001437438ca70, 9;
v000001437438ca70_10 .array/port v000001437438ca70, 10;
E_00000143742d7610/9 .event anyedge, v000001437438ca70_7, v000001437438ca70_8, v000001437438ca70_9, v000001437438ca70_10;
v000001437438ca70_11 .array/port v000001437438ca70, 11;
v000001437438ca70_12 .array/port v000001437438ca70, 12;
E_00000143742d7610/10 .event anyedge, v000001437438ca70_11, v000001437438ca70_12, v000001437438d6f0_0, v000001437438d6f0_1;
E_00000143742d7610/11 .event anyedge, v000001437438d6f0_2, v000001437438d6f0_3, v000001437438d6f0_4, v000001437438d6f0_5;
E_00000143742d7610/12 .event anyedge, v000001437438d6f0_6, v000001437438d6f0_7, v000001437438d6f0_8, v000001437438d6f0_9;
E_00000143742d7610/13 .event anyedge, v000001437438d6f0_10, v000001437438d6f0_11;
E_00000143742d7610 .event/or E_00000143742d7610/0, E_00000143742d7610/1, E_00000143742d7610/2, E_00000143742d7610/3, E_00000143742d7610/4, E_00000143742d7610/5, E_00000143742d7610/6, E_00000143742d7610/7, E_00000143742d7610/8, E_00000143742d7610/9, E_00000143742d7610/10, E_00000143742d7610/11, E_00000143742d7610/12, E_00000143742d7610/13;
L_0000014374406940 .extend/s 32, v000001437438d830_12;
L_0000014374407ac0 .arith/mult 32, L_0000014374406940, L_00000143743a9338;
L_00000143744077a0 .extend/s 32, v000001437438ca70_12;
L_0000014374408240 .arith/mult 32, L_00000143744077a0, L_00000143743a9380;
S_000001437438e450 .scope module, "u_sync" "sync_block" 4 45, 14 6 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "in_valid";
    .port_info 3 /INPUT 16 "in1_re";
    .port_info 4 /INPUT 16 "in1_im";
    .port_info 5 /INPUT 16 "in2_re";
    .port_info 6 /INPUT 16 "in2_im";
    .port_info 7 /OUTPUT 1 "out_valid";
    .port_info 8 /OUTPUT 1 "symbol_start";
    .port_info 9 /OUTPUT 16 "out1_re";
    .port_info 10 /OUTPUT 16 "out1_im";
    .port_info 11 /OUTPUT 16 "out2_re";
    .port_info 12 /OUTPUT 16 "out2_im";
    .port_info 13 /OUTPUT 5 "dbg_best_idx";
P_0000014373e0dcc0 .param/l "BUF_LEN" 1 14 27, +C4<00000000000000000000000000000000000000000000000000000000001100000>;
P_0000014373e0dcf8 .param/l "DATA_W" 0 14 7, +C4<00000000000000000000000000010000>;
P_0000014373e0dd30 .param/l "NCP" 0 14 9, +C4<00000000000000000000000000010000>;
P_0000014373e0dd68 .param/l "NFFT" 0 14 8, +C4<00000000000000000000000001000000>;
P_0000014373e0dda0 .param/l "SEARCH_MAX" 1 14 40, +C4<0000000000000000000000000000000000000000000000000000000000000010000>;
P_0000014373e0ddd8 .param/l "SYM_LEN" 1 14 28, +C4<000000000000000000000000001010000>;
P_0000014373e0de10 .param/l "S_CORR" 1 14 58, C4<010>;
P_0000014373e0de48 .param/l "S_FILL" 1 14 57, C4<001>;
P_0000014373e0de80 .param/l "S_IDLE" 1 14 56, C4<000>;
P_0000014373e0deb8 .param/l "S_STREAM" 1 14 59, C4<011>;
L_0000014374302350 .functor BUFZ 5, v00000143743957e0_0, C4<00000>, C4<00000>, C4<00000>;
L_0000014374304650 .functor BUFZ 16, L_00000143743a2a20, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_00000143743045e0 .functor BUFZ 16, L_00000143743a34c0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_00000143743043b0 .functor BUFZ 16, L_00000143743a31a0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374303e00 .functor BUFZ 16, L_00000143743a5680, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374304420 .functor BUFZ 16, L_00000143743a5b80, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374304730 .functor BUFZ 16, L_00000143743a5d60, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374303150 .functor BUFZ 16, L_00000143743a7020, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0000014374303850 .functor BUFZ 16, L_00000143743a75c0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_00000143743a84e0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374391a50_0 .net *"_ivl_101", 26 0, L_00000143743a84e0;  1 drivers
v00000143743917d0_0 .net *"_ivl_102", 31 0, L_00000143743a68a0;  1 drivers
L_00000143743a8528 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374391cd0_0 .net *"_ivl_105", 26 0, L_00000143743a8528;  1 drivers
v00000143743926d0_0 .net *"_ivl_106", 31 0, L_00000143743a7160;  1 drivers
L_00000143743a8570 .functor BUFT 1, C4<00000000000000000000000001000000>, C4<0>, C4<0>, C4<0>;
v0000014374391870_0 .net/2u *"_ivl_108", 31 0, L_00000143743a8570;  1 drivers
v0000014374391ff0_0 .net *"_ivl_110", 31 0, L_00000143743a59a0;  1 drivers
v0000014374390150_0 .net/s *"_ivl_114", 31 0, L_00000143743a7660;  1 drivers
v0000014374392770_0 .net/s *"_ivl_116", 31 0, L_00000143743a5cc0;  1 drivers
v0000014374391410_0 .net/s *"_ivl_119", 31 0, L_00000143743a52c0;  1 drivers
v0000014374391d70_0 .net *"_ivl_12", 15 0, L_00000143743a34c0;  1 drivers
v0000014374390b50_0 .net/s *"_ivl_120", 31 0, L_00000143743a5fe0;  1 drivers
v0000014374390dd0_0 .net/s *"_ivl_122", 31 0, L_00000143743a5360;  1 drivers
v0000014374390e70_0 .net/s *"_ivl_125", 31 0, L_00000143743a5860;  1 drivers
v0000014374392810_0 .net/s *"_ivl_128", 31 0, L_00000143743a5400;  1 drivers
v0000014374391b90_0 .net/s *"_ivl_130", 31 0, L_00000143743a78e0;  1 drivers
v00000143743912d0_0 .net/s *"_ivl_133", 31 0, L_00000143743a6080;  1 drivers
v00000143743914b0_0 .net/s *"_ivl_134", 31 0, L_00000143743a7840;  1 drivers
v00000143743924f0_0 .net/s *"_ivl_136", 31 0, L_00000143743a5ea0;  1 drivers
v00000143743928b0_0 .net/s *"_ivl_139", 31 0, L_00000143743a6d00;  1 drivers
v0000014374390a10_0 .net *"_ivl_14", 4 0, L_00000143743a2f20;  1 drivers
v0000014374391c30_0 .net/s *"_ivl_142", 31 0, L_00000143743a6120;  1 drivers
v0000014374391230_0 .net/s *"_ivl_144", 31 0, L_00000143743a6260;  1 drivers
v0000014374391e10_0 .net/s *"_ivl_147", 31 0, L_00000143743a5180;  1 drivers
v00000143743901f0_0 .net/s *"_ivl_148", 31 0, L_00000143743a6300;  1 drivers
v0000014374391730_0 .net/s *"_ivl_150", 31 0, L_00000143743a6940;  1 drivers
v0000014374391eb0_0 .net/s *"_ivl_153", 31 0, L_00000143743a5540;  1 drivers
v0000014374390790_0 .net/s *"_ivl_156", 31 0, L_00000143743a55e0;  1 drivers
v0000014374390290_0 .net/s *"_ivl_158", 31 0, L_00000143743a57c0;  1 drivers
v0000014374392310_0 .net *"_ivl_16", 7 0, L_00000143743a2fc0;  1 drivers
v0000014374391190_0 .net/s *"_ivl_161", 31 0, L_00000143743a70c0;  1 drivers
v0000014374392090_0 .net/s *"_ivl_162", 31 0, L_00000143743a69e0;  1 drivers
v00000143743915f0_0 .net/s *"_ivl_164", 31 0, L_00000143743a5f40;  1 drivers
v0000014374390330_0 .net/s *"_ivl_167", 31 0, L_00000143743a6b20;  1 drivers
v0000014374391910_0 .net/s *"_ivl_170", 32 0, L_00000143743a6440;  1 drivers
v0000014374391550_0 .net/s *"_ivl_172", 32 0, L_00000143743a64e0;  1 drivers
v0000014374391370_0 .net/s *"_ivl_176", 32 0, L_00000143743a7340;  1 drivers
v0000014374390c90_0 .net/s *"_ivl_178", 32 0, L_00000143743a6580;  1 drivers
v0000014374391f50_0 .net *"_ivl_183", 0 0, L_00000143743a73e0;  1 drivers
v00000143743903d0_0 .net *"_ivl_184", 14 0, L_00000143743a66c0;  1 drivers
v0000014374390510_0 .net *"_ivl_186", 47 0, L_00000143743a6760;  1 drivers
L_00000143743a8180 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v0000014374391690_0 .net *"_ivl_19", 2 0, L_00000143743a8180;  1 drivers
v0000014374392130_0 .net *"_ivl_191", 0 0, L_00000143743a6a80;  1 drivers
v00000143743919b0_0 .net *"_ivl_192", 14 0, L_00000143743a8060;  1 drivers
v00000143743921d0_0 .net *"_ivl_194", 47 0, L_00000143743a7f20;  1 drivers
v0000014374392590_0 .net/s *"_ivl_198", 95 0, L_00000143743a7e80;  1 drivers
v00000143743906f0_0 .net *"_ivl_2", 15 0, L_00000143743a2a20;  1 drivers
v0000014374390d30_0 .net/s *"_ivl_200", 95 0, L_00000143743a7de0;  1 drivers
v0000014374391af0_0 .net/s *"_ivl_203", 95 0, L_00000143743a7a20;  1 drivers
v0000014374390650_0 .net/s *"_ivl_204", 95 0, L_00000143743a7fc0;  1 drivers
v0000014374392270_0 .net/s *"_ivl_206", 95 0, L_00000143743a7ac0;  1 drivers
v0000014374390f10_0 .net/s *"_ivl_209", 95 0, L_00000143743a7980;  1 drivers
L_00000143743a85b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v00000143743923b0_0 .net/2u *"_ivl_212", 0 0, L_00000143743a85b8;  1 drivers
v00000143743905b0_0 .net *"_ivl_214", 96 0, L_00000143743a7ca0;  1 drivers
L_00000143743a8600 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0000014374390830_0 .net/2u *"_ivl_216", 0 0, L_00000143743a8600;  1 drivers
v00000143743908d0_0 .net *"_ivl_218", 95 0, L_00000143743a7d40;  1 drivers
v0000014374390ab0_0 .net *"_ivl_22", 15 0, L_00000143743a31a0;  1 drivers
v0000014374390bf0_0 .net *"_ivl_220", 5 0, L_00000143743a0680;  1 drivers
L_00000143743a8648 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v00000143743929f0_0 .net *"_ivl_223", 0 0, L_00000143743a8648;  1 drivers
v0000014374392f90_0 .net *"_ivl_224", 96 0, L_00000143743a0f40;  1 drivers
v0000014374392c70_0 .net *"_ivl_228", 95 0, L_00000143743a2340;  1 drivers
v00000143743938f0_0 .net *"_ivl_230", 5 0, L_00000143743a0720;  1 drivers
L_00000143743a8690 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0000014374393350_0 .net *"_ivl_233", 0 0, L_00000143743a8690;  1 drivers
v0000014374393990_0 .net *"_ivl_234", 96 0, L_00000143743a22a0;  1 drivers
L_00000143743a86d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v00000143743932b0_0 .net *"_ivl_237", 0 0, L_00000143743a86d8;  1 drivers
v0000014374393fd0_0 .net *"_ivl_238", 96 0, L_00000143743a1940;  1 drivers
v0000014374393b70_0 .net *"_ivl_24", 31 0, L_00000143743a6e40;  1 drivers
v0000014374393df0_0 .net *"_ivl_240", 92 0, L_00000143743a23e0;  1 drivers
L_00000143743a8720 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>;
v0000014374392d10_0 .net *"_ivl_242", 3 0, L_00000143743a8720;  1 drivers
v0000014374393710_0 .net *"_ivl_244", 96 0, L_00000143743a13a0;  1 drivers
L_00000143743a81c8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374393670_0 .net *"_ivl_27", 26 0, L_00000143743a81c8;  1 drivers
v00000143743937b0_0 .net *"_ivl_28", 31 0, L_00000143743a5a40;  1 drivers
L_00000143743a8210 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374392ef0_0 .net *"_ivl_31", 26 0, L_00000143743a8210;  1 drivers
v0000014374393490_0 .net *"_ivl_32", 31 0, L_00000143743a7480;  1 drivers
L_00000143743a8258 .functor BUFT 1, C4<00000000000000000000000001000000>, C4<0>, C4<0>, C4<0>;
v0000014374393850_0 .net/2u *"_ivl_34", 31 0, L_00000143743a8258;  1 drivers
v0000014374393d50_0 .net *"_ivl_36", 31 0, L_00000143743a6bc0;  1 drivers
v00000143743930d0_0 .net *"_ivl_4", 4 0, L_00000143743a4b40;  1 drivers
v0000014374392a90_0 .net *"_ivl_40", 15 0, L_00000143743a5680;  1 drivers
v0000014374393170_0 .net *"_ivl_42", 31 0, L_00000143743a6c60;  1 drivers
L_00000143743a82a0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374392b30_0 .net *"_ivl_45", 26 0, L_00000143743a82a0;  1 drivers
v0000014374393c10_0 .net *"_ivl_46", 31 0, L_00000143743a7700;  1 drivers
L_00000143743a82e8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374393a30_0 .net *"_ivl_49", 26 0, L_00000143743a82e8;  1 drivers
v0000014374393f30_0 .net *"_ivl_50", 31 0, L_00000143743a5720;  1 drivers
L_00000143743a8330 .functor BUFT 1, C4<00000000000000000000000001000000>, C4<0>, C4<0>, C4<0>;
v0000014374392950_0 .net/2u *"_ivl_52", 31 0, L_00000143743a8330;  1 drivers
v0000014374392bd0_0 .net *"_ivl_54", 31 0, L_00000143743a5220;  1 drivers
v0000014374393cb0_0 .net *"_ivl_58", 15 0, L_00000143743a5b80;  1 drivers
v0000014374393210_0 .net *"_ivl_6", 7 0, L_00000143743a2d40;  1 drivers
v0000014374393e90_0 .net *"_ivl_60", 4 0, L_00000143743a6ee0;  1 drivers
v0000014374392db0_0 .net *"_ivl_62", 7 0, L_00000143743a54a0;  1 drivers
L_00000143743a8378 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v0000014374392e50_0 .net *"_ivl_65", 2 0, L_00000143743a8378;  1 drivers
v0000014374393030_0 .net *"_ivl_68", 15 0, L_00000143743a5d60;  1 drivers
v00000143743933f0_0 .net *"_ivl_70", 4 0, L_00000143743a7520;  1 drivers
v0000014374393530_0 .net *"_ivl_72", 7 0, L_00000143743a72a0;  1 drivers
L_00000143743a83c0 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v00000143743935d0_0 .net *"_ivl_75", 2 0, L_00000143743a83c0;  1 drivers
v0000014374393ad0_0 .net *"_ivl_78", 15 0, L_00000143743a7020;  1 drivers
v0000014374396140_0 .net *"_ivl_80", 31 0, L_00000143743a5e00;  1 drivers
L_00000143743a8408 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374394a20_0 .net *"_ivl_83", 26 0, L_00000143743a8408;  1 drivers
v0000014374395d80_0 .net *"_ivl_84", 31 0, L_00000143743a5ae0;  1 drivers
L_00000143743a8450 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000014374395ec0_0 .net *"_ivl_87", 26 0, L_00000143743a8450;  1 drivers
v0000014374396780_0 .net *"_ivl_88", 31 0, L_00000143743a61c0;  1 drivers
L_00000143743a8138 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v0000014374395880_0 .net *"_ivl_9", 2 0, L_00000143743a8138;  1 drivers
L_00000143743a8498 .functor BUFT 1, C4<00000000000000000000000001000000>, C4<0>, C4<0>, C4<0>;
v0000014374394520_0 .net/2u *"_ivl_90", 31 0, L_00000143743a8498;  1 drivers
v0000014374395ce0_0 .net *"_ivl_92", 31 0, L_00000143743a5c20;  1 drivers
v0000014374394b60_0 .net *"_ivl_96", 15 0, L_00000143743a75c0;  1 drivers
v0000014374394de0_0 .net *"_ivl_98", 31 0, L_00000143743a5900;  1 drivers
v0000014374394e80_0 .net/s "a1_im", 15 0, L_00000143743045e0;  1 drivers
v0000014374396640_0 .net/s "a1_re", 15 0, L_0000014374304650;  1 drivers
v0000014374395ba0_0 .net/s "a2_im", 15 0, L_0000014374304730;  1 drivers
v00000143743952e0_0 .net/s "a2_re", 15 0, L_0000014374304420;  1 drivers
v0000014374395420_0 .net/s "b1_im", 15 0, L_0000014374303e00;  1 drivers
v0000014374396460_0 .net/s "b1_re", 15 0, L_00000143743043b0;  1 drivers
v0000014374394c00_0 .net/s "b2_im", 15 0, L_0000014374303850;  1 drivers
v0000014374394f20_0 .net/s "b2_re", 15 0, L_0000014374303150;  1 drivers
v00000143743957e0_0 .var "best_idx", 4 0;
v00000143743948e0_0 .var "best_metric", 95 0;
v0000014374395e20 .array/s "buf1_im", 95 0, 15 0;
v0000014374395a60 .array/s "buf1_re", 95 0, 15 0;
v00000143743966e0 .array/s "buf2_im", 95 0, 15 0;
v0000014374394660 .array/s "buf2_re", 95 0, 15 0;
v0000014374394fc0_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v0000014374395920_0 .net "dbg_best_idx", 4 0, L_0000014374302350;  1 drivers
v00000143743961e0_0 .net "ema_candidate", 95 0, L_00000143743a0220;  1 drivers
v0000014374395560_0 .net/s "ema_diff", 96 0, L_00000143743a27a0;  1 drivers
v0000014374394980_0 .var "fill_cnt", 6 0;
v0000014374396320_0 .var "i_idx", 4 0;
v0000014374394700_0 .net/s "in1_im", 15 0, v00000143743a4dc0_0;  alias, 1 drivers
v0000014374395f60_0 .net/s "in1_re", 15 0, v00000143743a4500_0;  alias, 1 drivers
v0000014374394ac0_0 .net/s "in2_im", 15 0, v00000143743a3380_0;  alias, 1 drivers
v0000014374396000_0 .net/s "in2_re", 15 0, v00000143743a3600_0;  alias, 1 drivers
v00000143743960a0_0 .net "in_valid", 0 0, v00000143743a4780_0;  alias, 1 drivers
v00000143743945c0_0 .var/i "j", 31 0;
v0000014374395060_0 .var "m_idx", 4 0;
v0000014374395380 .array "metric_ema", 16 0, 95 0;
v0000014374396280_0 .net "metric_next", 95 0, L_00000143743a7c00;  1 drivers
v0000014374394200_0 .var/s "out1_im", 15 0;
v0000014374396820_0 .var/s "out1_re", 15 0;
v0000014374395100_0 .var/s "out2_im", 15 0;
v00000143743963c0_0 .var/s "out2_re", 15 0;
v00000143743959c0_0 .var "out_idx", 6 0;
v0000014374396500_0 .var "out_valid", 0 0;
v00000143743965a0_0 .net/s "p1_im", 31 0, L_00000143743a6f80;  1 drivers
v00000143743968c0_0 .net/s "p1_re", 31 0, L_00000143743a77a0;  1 drivers
v0000014374394160_0 .net/s "p2_im", 31 0, L_00000143743a6da0;  1 drivers
v00000143743942a0_0 .net/s "p2_re", 31 0, L_00000143743a63a0;  1 drivers
v0000014374394340_0 .net/s "p_im", 32 0, L_00000143743a6620;  1 drivers
v0000014374394ca0_0 .net/s "p_re", 32 0, L_00000143743a7200;  1 drivers
v00000143743943e0_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
v00000143743951a0_0 .var "state", 2 0;
v0000014374395240_0 .var/s "sum_im", 47 0;
v0000014374394480_0 .net/s "sum_im_next", 47 0, L_00000143743a7b60;  1 drivers
v0000014374394840_0 .var/s "sum_re", 47 0;
v0000014374395b00_0 .net/s "sum_re_next", 47 0, L_00000143743a6800;  1 drivers
v00000143743947a0_0 .var "symbol_start", 0 0;
L_00000143743a2a20 .array/port v0000014374395a60, L_00000143743a2d40;
L_00000143743a4b40 .arith/sum 5, v0000014374395060_0, v0000014374396320_0;
L_00000143743a2d40 .concat [ 5 3 0 0], L_00000143743a4b40, L_00000143743a8138;
L_00000143743a34c0 .array/port v0000014374395e20, L_00000143743a2fc0;
L_00000143743a2f20 .arith/sum 5, v0000014374395060_0, v0000014374396320_0;
L_00000143743a2fc0 .concat [ 5 3 0 0], L_00000143743a2f20, L_00000143743a8180;
L_00000143743a31a0 .array/port v0000014374395a60, L_00000143743a6bc0;
L_00000143743a6e40 .concat [ 5 27 0 0], v0000014374395060_0, L_00000143743a81c8;
L_00000143743a5a40 .concat [ 5 27 0 0], v0000014374396320_0, L_00000143743a8210;
L_00000143743a7480 .arith/sum 32, L_00000143743a6e40, L_00000143743a5a40;
L_00000143743a6bc0 .arith/sum 32, L_00000143743a7480, L_00000143743a8258;
L_00000143743a5680 .array/port v0000014374395e20, L_00000143743a5220;
L_00000143743a6c60 .concat [ 5 27 0 0], v0000014374395060_0, L_00000143743a82a0;
L_00000143743a7700 .concat [ 5 27 0 0], v0000014374396320_0, L_00000143743a82e8;
L_00000143743a5720 .arith/sum 32, L_00000143743a6c60, L_00000143743a7700;
L_00000143743a5220 .arith/sum 32, L_00000143743a5720, L_00000143743a8330;
L_00000143743a5b80 .array/port v0000014374394660, L_00000143743a54a0;
L_00000143743a6ee0 .arith/sum 5, v0000014374395060_0, v0000014374396320_0;
L_00000143743a54a0 .concat [ 5 3 0 0], L_00000143743a6ee0, L_00000143743a8378;
L_00000143743a5d60 .array/port v00000143743966e0, L_00000143743a72a0;
L_00000143743a7520 .arith/sum 5, v0000014374395060_0, v0000014374396320_0;
L_00000143743a72a0 .concat [ 5 3 0 0], L_00000143743a7520, L_00000143743a83c0;
L_00000143743a7020 .array/port v0000014374394660, L_00000143743a5c20;
L_00000143743a5e00 .concat [ 5 27 0 0], v0000014374395060_0, L_00000143743a8408;
L_00000143743a5ae0 .concat [ 5 27 0 0], v0000014374396320_0, L_00000143743a8450;
L_00000143743a61c0 .arith/sum 32, L_00000143743a5e00, L_00000143743a5ae0;
L_00000143743a5c20 .arith/sum 32, L_00000143743a61c0, L_00000143743a8498;
L_00000143743a75c0 .array/port v00000143743966e0, L_00000143743a59a0;
L_00000143743a5900 .concat [ 5 27 0 0], v0000014374395060_0, L_00000143743a84e0;
L_00000143743a68a0 .concat [ 5 27 0 0], v0000014374396320_0, L_00000143743a8528;
L_00000143743a7160 .arith/sum 32, L_00000143743a5900, L_00000143743a68a0;
L_00000143743a59a0 .arith/sum 32, L_00000143743a7160, L_00000143743a8570;
L_00000143743a7660 .extend/s 32, L_0000014374304650;
L_00000143743a5cc0 .extend/s 32, L_00000143743043b0;
L_00000143743a52c0 .arith/mult 32, L_00000143743a7660, L_00000143743a5cc0;
L_00000143743a5fe0 .extend/s 32, L_00000143743045e0;
L_00000143743a5360 .extend/s 32, L_0000014374303e00;
L_00000143743a5860 .arith/mult 32, L_00000143743a5fe0, L_00000143743a5360;
L_00000143743a77a0 .arith/sum 32, L_00000143743a52c0, L_00000143743a5860;
L_00000143743a5400 .extend/s 32, L_00000143743045e0;
L_00000143743a78e0 .extend/s 32, L_00000143743043b0;
L_00000143743a6080 .arith/mult 32, L_00000143743a5400, L_00000143743a78e0;
L_00000143743a7840 .extend/s 32, L_0000014374304650;
L_00000143743a5ea0 .extend/s 32, L_0000014374303e00;
L_00000143743a6d00 .arith/mult 32, L_00000143743a7840, L_00000143743a5ea0;
L_00000143743a6f80 .arith/sub 32, L_00000143743a6080, L_00000143743a6d00;
L_00000143743a6120 .extend/s 32, L_0000014374304420;
L_00000143743a6260 .extend/s 32, L_0000014374303150;
L_00000143743a5180 .arith/mult 32, L_00000143743a6120, L_00000143743a6260;
L_00000143743a6300 .extend/s 32, L_0000014374304730;
L_00000143743a6940 .extend/s 32, L_0000014374303850;
L_00000143743a5540 .arith/mult 32, L_00000143743a6300, L_00000143743a6940;
L_00000143743a63a0 .arith/sum 32, L_00000143743a5180, L_00000143743a5540;
L_00000143743a55e0 .extend/s 32, L_0000014374304730;
L_00000143743a57c0 .extend/s 32, L_0000014374303150;
L_00000143743a70c0 .arith/mult 32, L_00000143743a55e0, L_00000143743a57c0;
L_00000143743a69e0 .extend/s 32, L_0000014374304420;
L_00000143743a5f40 .extend/s 32, L_0000014374303850;
L_00000143743a6b20 .arith/mult 32, L_00000143743a69e0, L_00000143743a5f40;
L_00000143743a6da0 .arith/sub 32, L_00000143743a70c0, L_00000143743a6b20;
L_00000143743a6440 .extend/s 33, L_00000143743a77a0;
L_00000143743a64e0 .extend/s 33, L_00000143743a63a0;
L_00000143743a7200 .arith/sum 33, L_00000143743a6440, L_00000143743a64e0;
L_00000143743a7340 .extend/s 33, L_00000143743a6f80;
L_00000143743a6580 .extend/s 33, L_00000143743a6da0;
L_00000143743a6620 .arith/sum 33, L_00000143743a7340, L_00000143743a6580;
L_00000143743a73e0 .part L_00000143743a7200, 32, 1;
LS_00000143743a66c0_0_0 .concat [ 1 1 1 1], L_00000143743a73e0, L_00000143743a73e0, L_00000143743a73e0, L_00000143743a73e0;
LS_00000143743a66c0_0_4 .concat [ 1 1 1 1], L_00000143743a73e0, L_00000143743a73e0, L_00000143743a73e0, L_00000143743a73e0;
LS_00000143743a66c0_0_8 .concat [ 1 1 1 1], L_00000143743a73e0, L_00000143743a73e0, L_00000143743a73e0, L_00000143743a73e0;
LS_00000143743a66c0_0_12 .concat [ 1 1 1 0], L_00000143743a73e0, L_00000143743a73e0, L_00000143743a73e0;
L_00000143743a66c0 .concat [ 4 4 4 3], LS_00000143743a66c0_0_0, LS_00000143743a66c0_0_4, LS_00000143743a66c0_0_8, LS_00000143743a66c0_0_12;
L_00000143743a6760 .concat [ 33 15 0 0], L_00000143743a7200, L_00000143743a66c0;
L_00000143743a6800 .arith/sum 48, v0000014374394840_0, L_00000143743a6760;
L_00000143743a6a80 .part L_00000143743a6620, 32, 1;
LS_00000143743a8060_0_0 .concat [ 1 1 1 1], L_00000143743a6a80, L_00000143743a6a80, L_00000143743a6a80, L_00000143743a6a80;
LS_00000143743a8060_0_4 .concat [ 1 1 1 1], L_00000143743a6a80, L_00000143743a6a80, L_00000143743a6a80, L_00000143743a6a80;
LS_00000143743a8060_0_8 .concat [ 1 1 1 1], L_00000143743a6a80, L_00000143743a6a80, L_00000143743a6a80, L_00000143743a6a80;
LS_00000143743a8060_0_12 .concat [ 1 1 1 0], L_00000143743a6a80, L_00000143743a6a80, L_00000143743a6a80;
L_00000143743a8060 .concat [ 4 4 4 3], LS_00000143743a8060_0_0, LS_00000143743a8060_0_4, LS_00000143743a8060_0_8, LS_00000143743a8060_0_12;
L_00000143743a7f20 .concat [ 33 15 0 0], L_00000143743a6620, L_00000143743a8060;
L_00000143743a7b60 .arith/sum 48, v0000014374395240_0, L_00000143743a7f20;
L_00000143743a7e80 .extend/s 96, L_00000143743a6800;
L_00000143743a7de0 .extend/s 96, L_00000143743a6800;
L_00000143743a7a20 .arith/mult 96, L_00000143743a7e80, L_00000143743a7de0;
L_00000143743a7fc0 .extend/s 96, L_00000143743a7b60;
L_00000143743a7ac0 .extend/s 96, L_00000143743a7b60;
L_00000143743a7980 .arith/mult 96, L_00000143743a7fc0, L_00000143743a7ac0;
L_00000143743a7c00 .arith/sum 96, L_00000143743a7a20, L_00000143743a7980;
L_00000143743a7ca0 .concat [ 96 1 0 0], L_00000143743a7c00, L_00000143743a85b8;
L_00000143743a7d40 .array/port v0000014374395380, L_00000143743a0680;
L_00000143743a0680 .concat [ 5 1 0 0], v0000014374395060_0, L_00000143743a8648;
L_00000143743a0f40 .concat [ 96 1 0 0], L_00000143743a7d40, L_00000143743a8600;
L_00000143743a27a0 .arith/sub 97, L_00000143743a7ca0, L_00000143743a0f40;
L_00000143743a2340 .array/port v0000014374395380, L_00000143743a0720;
L_00000143743a0720 .concat [ 5 1 0 0], v0000014374395060_0, L_00000143743a8690;
L_00000143743a22a0 .concat [ 96 1 0 0], L_00000143743a2340, L_00000143743a86d8;
L_00000143743a23e0 .part L_00000143743a27a0, 4, 93;
L_00000143743a1940 .concat [ 93 4 0 0], L_00000143743a23e0, L_00000143743a8720;
L_00000143743a13a0 .arith/sum 97, L_00000143743a22a0, L_00000143743a1940;
L_00000143743a0220 .part L_00000143743a13a0, 0, 96;
S_000001437438f260 .scope module, "u_zf" "mimo_zf_2x2" 4 352, 15 1 0, S_0000014374323130;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 1 "in_valid";
    .port_info 3 /INPUT 16 "Y1_re";
    .port_info 4 /INPUT 16 "Y1_im";
    .port_info 5 /INPUT 16 "Y2_re";
    .port_info 6 /INPUT 16 "Y2_im";
    .port_info 7 /INPUT 16 "h00_re";
    .port_info 8 /INPUT 16 "h00_im";
    .port_info 9 /INPUT 16 "h01_re";
    .port_info 10 /INPUT 16 "h01_im";
    .port_info 11 /INPUT 16 "h10_re";
    .port_info 12 /INPUT 16 "h10_im";
    .port_info 13 /INPUT 16 "h11_re";
    .port_info 14 /INPUT 16 "h11_im";
    .port_info 15 /OUTPUT 1 "out_valid";
    .port_info 16 /OUTPUT 16 "X1_re";
    .port_info 17 /OUTPUT 16 "X1_im";
    .port_info 18 /OUTPUT 16 "X2_re";
    .port_info 19 /OUTPUT 16 "X2_im";
P_0000014373d4b1d0 .param/l "DATA_W" 0 15 2, +C4<00000000000000000000000000010000>;
P_0000014373d4b208 .param/l "FRAC" 0 15 3, +C4<00000000000000000000000000001011>;
v000001437439f5b0_0 .var/s "X1_im", 15 0;
v000001437439d210_0 .var/s "X1_re", 15 0;
v000001437439d2b0_0 .var/s "X2_im", 15 0;
v000001437439ee30_0 .var/s "X2_re", 15 0;
v000001437439d350_0 .net/s "Y1_im", 15 0, v000001437439a3d0_0;  1 drivers
v000001437439f010_0 .net/s "Y1_re", 15 0, v0000014374398490_0;  1 drivers
v000001437439de90_0 .net/s "Y2_im", 15 0, v00000143743983f0_0;  1 drivers
v000001437439dd50_0 .net/s "Y2_re", 15 0, v0000014374399390_0;  1 drivers
v000001437439f650_0 .net "clk", 0 0, v00000143743a3ba0_0;  alias, 1 drivers
v000001437439f0b0_0 .net/s "h00_im", 15 0, v00000143743a37e0_0;  alias, 1 drivers
v000001437439f1f0_0 .net/s "h00_re", 15 0, v00000143743a46e0_0;  alias, 1 drivers
v000001437439dad0_0 .net/s "h01_im", 15 0, v00000143743a4960_0;  alias, 1 drivers
v000001437439f290_0 .net/s "h01_re", 15 0, v00000143743a2980_0;  alias, 1 drivers
v000001437439f330_0 .net/s "h10_im", 15 0, v00000143743a4fa0_0;  alias, 1 drivers
v000001437439d3f0_0 .net/s "h10_re", 15 0, v00000143743a3100_0;  alias, 1 drivers
v000001437439f3d0_0 .net/s "h11_im", 15 0, v00000143743a3c40_0;  alias, 1 drivers
v000001437439f470_0 .net/s "h11_re", 15 0, v00000143743a3880_0;  alias, 1 drivers
v000001437439d8f0_0 .net "in_valid", 0 0, v0000014374399ed0_0;  1 drivers
v000001437439db70_0 .var "out_valid", 0 0;
v000001437439e110_0 .net/s "p00_im", 15 0, v0000014374396be0_0;  1 drivers
v000001437439dc10_0 .net/s "p00_re", 15 0, v00000143743975e0_0;  1 drivers
v000001437439f6f0_0 .net/s "p01_im", 15 0, v000001437439b9b0_0;  1 drivers
v000001437439ebb0_0 .net/s "p01_re", 15 0, v000001437439b4b0_0;  1 drivers
v000001437439df30_0 .net/s "p10_im", 15 0, v000001437439d0d0_0;  1 drivers
v000001437439f790_0 .net/s "p10_re", 15 0, v000001437439baf0_0;  1 drivers
v000001437439d710_0 .net/s "p11_im", 15 0, v000001437439da30_0;  1 drivers
v000001437439dfd0_0 .net/s "p11_re", 15 0, v000001437439ed90_0;  1 drivers
v000001437439f830_0 .net "rst_n", 0 0, v00000143743a4820_0;  alias, 1 drivers
S_000001437438e5e0 .scope function.vec4.u16, "sat_add" "sat_add" 15 72, 15 72 0, S_000001437438f260;
 .timescale -9 -12;
v0000014374394d40_0 .var/s "a", 15 0;
v00000143743954c0_0 .var/s "b", 15 0;
v0000014374395600_0 .var/s "max_limit", 16 0;
v00000143743956a0_0 .var/s "min_limit", 16 0;
; Variable sat_add is vec4 return value of scope S_000001437438e5e0
v0000014374395c40_0 .var/s "sum", 16 0;
TD_tb_top_receiver.u_top.u_zf.sat_add ;
    %load/vec4 v0000014374394d40_0;
    %pad/s 17;
    %load/vec4 v00000143743954c0_0;
    %pad/s 17;
    %add;
    %store/vec4 v0000014374395c40_0, 0, 17;
    %pushi/vec4 32767, 0, 17;
    %store/vec4 v0000014374395600_0, 0, 17;
    %pushi/vec4 98304, 0, 17;
    %store/vec4 v00000143743956a0_0, 0, 17;
    %load/vec4 v0000014374395600_0;
    %load/vec4 v0000014374395c40_0;
    %cmp/s;
    %jmp/0xz  T_14.66, 5;
    %load/vec4 v0000014374395600_0;
    %parti/s 16, 0, 2;
    %ret/vec4 0, 0, 16;  Assign to sat_add (store_vec4_to_lval)
    %jmp T_14.67;
T_14.66 ;
    %load/vec4 v0000014374395c40_0;
    %load/vec4 v00000143743956a0_0;
    %cmp/s;
    %jmp/0xz  T_14.68, 5;
    %load/vec4 v00000143743956a0_0;
    %parti/s 16, 0, 2;
    %ret/vec4 0, 0, 16;  Assign to sat_add (store_vec4_to_lval)
    %jmp T_14.69;
T_14.68 ;
    %load/vec4 v0000014374395c40_0;
    %parti/s 16, 0, 2;
    %ret/vec4 0, 0, 16;  Assign to sat_add (store_vec4_to_lval)
T_14.69 ;
T_14.67 ;
    %end;
S_000001437438e900 .scope module, "u_mul_00" "complex_mult" 15 46, 6 1 0, S_000001437438f260;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "a_re";
    .port_info 1 /INPUT 16 "a_im";
    .port_info 2 /INPUT 16 "b_re";
    .port_info 3 /INPUT 16 "b_im";
    .port_info 4 /OUTPUT 16 "p_re";
    .port_info 5 /OUTPUT 16 "p_im";
P_0000014373e02840 .param/l "FRAC" 0 6 3, +C4<00000000000000000000000000001011>;
P_0000014373e02878 .param/l "MAX_VAL" 1 6 28, +C4<0111111111111111>;
P_0000014373e028b0 .param/l "MIN_VAL" 1 6 29, +C4<1000000000000000>;
P_0000014373e028e8 .param/l "WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
v0000014374397040_0 .net/s *"_ivl_0", 31 0, L_0000014374408420;  1 drivers
v0000014374397e00_0 .net/s *"_ivl_12", 31 0, L_0000014374407340;  1 drivers
v0000014374397c20_0 .net/s *"_ivl_14", 31 0, L_0000014374406d00;  1 drivers
v0000014374397ea0_0 .net/s *"_ivl_18", 31 0, L_00000143744086a0;  1 drivers
v0000014374397f40_0 .net/s *"_ivl_2", 31 0, L_00000143744063a0;  1 drivers
v0000014374397ae0_0 .net/s *"_ivl_20", 31 0, L_0000014374407520;  1 drivers
v00000143743970e0_0 .net/s *"_ivl_24", 32 0, L_00000143744075c0;  1 drivers
v0000014374397180_0 .net/s *"_ivl_26", 32 0, L_0000014374407660;  1 drivers
v0000014374396960_0 .net/s *"_ivl_30", 32 0, L_0000014374406bc0;  1 drivers
v0000014374397360_0 .net/s *"_ivl_32", 32 0, L_00000143744069e0;  1 drivers
v0000014374397fe0_0 .net *"_ivl_38", 21 0, L_0000014374407700;  1 drivers
v0000014374396f00_0 .net *"_ivl_42", 21 0, L_0000014374406300;  1 drivers
v0000014374397220_0 .net/s *"_ivl_6", 31 0, L_0000014374407980;  1 drivers
v00000143743972c0_0 .net/s *"_ivl_8", 31 0, L_0000014374408920;  1 drivers
v0000014374397680_0 .net/s "a_im", 15 0, v00000143743a37e0_0;  alias, 1 drivers
v0000014374397400_0 .net/s "a_re", 15 0, v00000143743a46e0_0;  alias, 1 drivers
v0000014374397860_0 .net/s "ac", 31 0, L_0000014374408560;  1 drivers
v0000014374397720_0 .net/s "ad", 31 0, L_0000014374408600;  1 drivers
v00000143743977c0_0 .net/s "b_im", 15 0, v000001437439a3d0_0;  alias, 1 drivers
v0000014374396fa0_0 .net/s "b_re", 15 0, v0000014374398490_0;  alias, 1 drivers
v0000014374397540_0 .net/s "bc", 31 0, L_0000014374406c60;  1 drivers
v0000014374397900_0 .net/s "bd", 31 0, L_00000143744072a0;  1 drivers
v0000014374396a00_0 .net/s "im_long", 32 0, L_0000014374406260;  1 drivers
v00000143743974a0_0 .net/s "im_shifted", 32 0, L_0000014374406440;  1 drivers
v0000014374396be0_0 .var/s "p_im", 15 0;
v00000143743975e0_0 .var/s "p_re", 15 0;
v0000014374396c80_0 .net/s "re_long", 32 0, L_00000143744061c0;  1 drivers
v0000014374397d60_0 .net/s "re_shifted", 32 0, L_0000014374407a20;  1 drivers
E_00000143742d76d0 .event anyedge, v0000014374397d60_0, v00000143743974a0_0;
L_0000014374408420 .extend/s 32, v00000143743a46e0_0;
L_00000143744063a0 .extend/s 32, v0000014374398490_0;
L_0000014374408560 .arith/mult 32, L_0000014374408420, L_00000143744063a0;
L_0000014374407980 .extend/s 32, v00000143743a37e0_0;
L_0000014374408920 .extend/s 32, v000001437439a3d0_0;
L_00000143744072a0 .arith/mult 32, L_0000014374407980, L_0000014374408920;
L_0000014374407340 .extend/s 32, v00000143743a46e0_0;
L_0000014374406d00 .extend/s 32, v000001437439a3d0_0;
L_0000014374408600 .arith/mult 32, L_0000014374407340, L_0000014374406d00;
L_00000143744086a0 .extend/s 32, v00000143743a37e0_0;
L_0000014374407520 .extend/s 32, v0000014374398490_0;
L_0000014374406c60 .arith/mult 32, L_00000143744086a0, L_0000014374407520;
L_00000143744075c0 .extend/s 33, L_0000014374408560;
L_0000014374407660 .extend/s 33, L_00000143744072a0;
L_00000143744061c0 .arith/sub 33, L_00000143744075c0, L_0000014374407660;
L_0000014374406bc0 .extend/s 33, L_0000014374408600;
L_00000143744069e0 .extend/s 33, L_0000014374406c60;
L_0000014374406260 .arith/sum 33, L_0000014374406bc0, L_00000143744069e0;
L_0000014374407700 .part L_00000143744061c0, 11, 22;
L_0000014374407a20 .extend/s 33, L_0000014374407700;
L_0000014374406300 .part L_0000014374406260, 11, 22;
L_0000014374406440 .extend/s 33, L_0000014374406300;
S_000001437438e130 .scope module, "u_mul_01" "complex_mult" 15 51, 6 1 0, S_000001437438f260;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "a_re";
    .port_info 1 /INPUT 16 "a_im";
    .port_info 2 /INPUT 16 "b_re";
    .port_info 3 /INPUT 16 "b_im";
    .port_info 4 /OUTPUT 16 "p_re";
    .port_info 5 /OUTPUT 16 "p_im";
P_0000014373e02930 .param/l "FRAC" 0 6 3, +C4<00000000000000000000000000001011>;
P_0000014373e02968 .param/l "MAX_VAL" 1 6 28, +C4<0111111111111111>;
P_0000014373e029a0 .param/l "MIN_VAL" 1 6 29, +C4<1000000000000000>;
P_0000014373e029d8 .param/l "WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
v0000014374396aa0_0 .net/s *"_ivl_0", 31 0, L_0000014374407b60;  1 drivers
v00000143743979a0_0 .net/s *"_ivl_12", 31 0, L_00000143744068a0;  1 drivers
v0000014374396b40_0 .net/s *"_ivl_14", 31 0, L_0000014374406b20;  1 drivers
v0000014374396d20_0 .net/s *"_ivl_18", 31 0, L_0000014374408a60;  1 drivers
v0000014374396dc0_0 .net/s *"_ivl_2", 31 0, L_0000014374407ca0;  1 drivers
v0000014374397a40_0 .net/s *"_ivl_20", 31 0, L_0000014374408f60;  1 drivers
v0000014374396e60_0 .net/s *"_ivl_24", 32 0, L_0000014374408ce0;  1 drivers
v0000014374397b80_0 .net/s *"_ivl_26", 32 0, L_0000014374409000;  1 drivers
v0000014374397cc0_0 .net/s *"_ivl_30", 32 0, L_00000143744090a0;  1 drivers
v000001437439cdb0_0 .net/s *"_ivl_32", 32 0, L_0000014374408ba0;  1 drivers
v000001437439c6d0_0 .net *"_ivl_38", 21 0, L_0000014374408e20;  1 drivers
v000001437439c8b0_0 .net *"_ivl_42", 21 0, L_0000014374403600;  1 drivers
v000001437439b910_0 .net/s *"_ivl_6", 31 0, L_0000014374406580;  1 drivers
v000001437439b410_0 .net/s *"_ivl_8", 31 0, L_0000014374406620;  1 drivers
v000001437439c630_0 .net/s "a_im", 15 0, v00000143743a4960_0;  alias, 1 drivers
v000001437439c3b0_0 .net/s "a_re", 15 0, v00000143743a2980_0;  alias, 1 drivers
v000001437439b550_0 .net/s "ac", 31 0, L_00000143744064e0;  1 drivers
v000001437439bc30_0 .net/s "ad", 31 0, L_00000143744089c0;  1 drivers
v000001437439cc70_0 .net/s "b_im", 15 0, v00000143743983f0_0;  alias, 1 drivers
v000001437439b370_0 .net/s "b_re", 15 0, v0000014374399390_0;  alias, 1 drivers
v000001437439b690_0 .net/s "bc", 31 0, L_0000014374408ec0;  1 drivers
v000001437439ce50_0 .net/s "bd", 31 0, L_0000014374406760;  1 drivers
v000001437439c770_0 .net/s "im_long", 32 0, L_0000014374408c40;  1 drivers
v000001437439c950_0 .net/s "im_shifted", 32 0, L_0000014374403060;  1 drivers
v000001437439b9b0_0 .var/s "p_im", 15 0;
v000001437439b4b0_0 .var/s "p_re", 15 0;
v000001437439c810_0 .net/s "re_long", 32 0, L_0000014374408b00;  1 drivers
v000001437439c450_0 .net/s "re_shifted", 32 0, L_0000014374408d80;  1 drivers
E_00000143742d7650 .event anyedge, v000001437439c450_0, v000001437439c950_0;
L_0000014374407b60 .extend/s 32, v00000143743a2980_0;
L_0000014374407ca0 .extend/s 32, v0000014374399390_0;
L_00000143744064e0 .arith/mult 32, L_0000014374407b60, L_0000014374407ca0;
L_0000014374406580 .extend/s 32, v00000143743a4960_0;
L_0000014374406620 .extend/s 32, v00000143743983f0_0;
L_0000014374406760 .arith/mult 32, L_0000014374406580, L_0000014374406620;
L_00000143744068a0 .extend/s 32, v00000143743a2980_0;
L_0000014374406b20 .extend/s 32, v00000143743983f0_0;
L_00000143744089c0 .arith/mult 32, L_00000143744068a0, L_0000014374406b20;
L_0000014374408a60 .extend/s 32, v00000143743a4960_0;
L_0000014374408f60 .extend/s 32, v0000014374399390_0;
L_0000014374408ec0 .arith/mult 32, L_0000014374408a60, L_0000014374408f60;
L_0000014374408ce0 .extend/s 33, L_00000143744064e0;
L_0000014374409000 .extend/s 33, L_0000014374406760;
L_0000014374408b00 .arith/sub 33, L_0000014374408ce0, L_0000014374409000;
L_00000143744090a0 .extend/s 33, L_00000143744089c0;
L_0000014374408ba0 .extend/s 33, L_0000014374408ec0;
L_0000014374408c40 .arith/sum 33, L_00000143744090a0, L_0000014374408ba0;
L_0000014374408e20 .part L_0000014374408b00, 11, 22;
L_0000014374408d80 .extend/s 33, L_0000014374408e20;
L_0000014374403600 .part L_0000014374408c40, 11, 22;
L_0000014374403060 .extend/s 33, L_0000014374403600;
S_000001437438fd50 .scope module, "u_mul_10" "complex_mult" 15 57, 6 1 0, S_000001437438f260;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "a_re";
    .port_info 1 /INPUT 16 "a_im";
    .port_info 2 /INPUT 16 "b_re";
    .port_info 3 /INPUT 16 "b_im";
    .port_info 4 /OUTPUT 16 "p_re";
    .port_info 5 /OUTPUT 16 "p_im";
P_0000014373e02a20 .param/l "FRAC" 0 6 3, +C4<00000000000000000000000000001011>;
P_0000014373e02a58 .param/l "MAX_VAL" 1 6 28, +C4<0111111111111111>;
P_0000014373e02a90 .param/l "MIN_VAL" 1 6 29, +C4<1000000000000000>;
P_0000014373e02ac8 .param/l "WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
v000001437439cef0_0 .net/s *"_ivl_0", 31 0, L_00000143744027a0;  1 drivers
v000001437439b730_0 .net/s *"_ivl_12", 31 0, L_0000014374402840;  1 drivers
v000001437439c9f0_0 .net/s *"_ivl_14", 31 0, L_0000014374401da0;  1 drivers
v000001437439cf90_0 .net/s *"_ivl_18", 31 0, L_0000014374402d40;  1 drivers
v000001437439cb30_0 .net/s *"_ivl_2", 31 0, L_0000014374401b20;  1 drivers
v000001437439ae70_0 .net/s *"_ivl_20", 31 0, L_00000143744020c0;  1 drivers
v000001437439ac90_0 .net/s *"_ivl_24", 32 0, L_00000143744028e0;  1 drivers
v000001437439ca90_0 .net/s *"_ivl_26", 32 0, L_00000143744014e0;  1 drivers
v000001437439b230_0 .net/s *"_ivl_30", 32 0, L_0000014374403560;  1 drivers
v000001437439c590_0 .net/s *"_ivl_32", 32 0, L_00000143744037e0;  1 drivers
v000001437439c130_0 .net *"_ivl_38", 21 0, L_0000014374401ee0;  1 drivers
v000001437439b5f0_0 .net *"_ivl_42", 21 0, L_0000014374401f80;  1 drivers
v000001437439b870_0 .net/s *"_ivl_6", 31 0, L_00000143744034c0;  1 drivers
v000001437439b7d0_0 .net/s *"_ivl_8", 31 0, L_0000014374402200;  1 drivers
v000001437439c310_0 .net/s "a_im", 15 0, v00000143743a4fa0_0;  alias, 1 drivers
v000001437439cbd0_0 .net/s "a_re", 15 0, v00000143743a3100_0;  alias, 1 drivers
v000001437439b0f0_0 .net/s "ac", 31 0, L_0000014374403100;  1 drivers
v000001437439c1d0_0 .net/s "ad", 31 0, L_0000014374402ac0;  1 drivers
v000001437439cd10_0 .net/s "b_im", 15 0, v000001437439a3d0_0;  alias, 1 drivers
v000001437439d030_0 .net/s "b_re", 15 0, v0000014374398490_0;  alias, 1 drivers
v000001437439af10_0 .net/s "bc", 31 0, L_0000014374402020;  1 drivers
v000001437439ba50_0 .net/s "bd", 31 0, L_0000014374403920;  1 drivers
v000001437439beb0_0 .net/s "im_long", 32 0, L_00000143744019e0;  1 drivers
v000001437439afb0_0 .net/s "im_shifted", 32 0, L_00000143744022a0;  1 drivers
v000001437439d0d0_0 .var/s "p_im", 15 0;
v000001437439baf0_0 .var/s "p_re", 15 0;
v000001437439bb90_0 .net/s "re_long", 32 0, L_0000014374401580;  1 drivers
v000001437439aa10_0 .net/s "re_shifted", 32 0, L_0000014374402c00;  1 drivers
E_00000143742d8190 .event anyedge, v000001437439aa10_0, v000001437439afb0_0;
L_00000143744027a0 .extend/s 32, v00000143743a3100_0;
L_0000014374401b20 .extend/s 32, v0000014374398490_0;
L_0000014374403100 .arith/mult 32, L_00000143744027a0, L_0000014374401b20;
L_00000143744034c0 .extend/s 32, v00000143743a4fa0_0;
L_0000014374402200 .extend/s 32, v000001437439a3d0_0;
L_0000014374403920 .arith/mult 32, L_00000143744034c0, L_0000014374402200;
L_0000014374402840 .extend/s 32, v00000143743a3100_0;
L_0000014374401da0 .extend/s 32, v000001437439a3d0_0;
L_0000014374402ac0 .arith/mult 32, L_0000014374402840, L_0000014374401da0;
L_0000014374402d40 .extend/s 32, v00000143743a4fa0_0;
L_00000143744020c0 .extend/s 32, v0000014374398490_0;
L_0000014374402020 .arith/mult 32, L_0000014374402d40, L_00000143744020c0;
L_00000143744028e0 .extend/s 33, L_0000014374403100;
L_00000143744014e0 .extend/s 33, L_0000014374403920;
L_0000014374401580 .arith/sub 33, L_00000143744028e0, L_00000143744014e0;
L_0000014374403560 .extend/s 33, L_0000014374402ac0;
L_00000143744037e0 .extend/s 33, L_0000014374402020;
L_00000143744019e0 .arith/sum 33, L_0000014374403560, L_00000143744037e0;
L_0000014374401ee0 .part L_0000014374401580, 11, 22;
L_0000014374402c00 .extend/s 33, L_0000014374401ee0;
L_0000014374401f80 .part L_00000143744019e0, 11, 22;
L_00000143744022a0 .extend/s 33, L_0000014374401f80;
S_000001437438ec20 .scope module, "u_mul_11" "complex_mult" 15 62, 6 1 0, S_000001437438f260;
 .timescale -9 -12;
    .port_info 0 /INPUT 16 "a_re";
    .port_info 1 /INPUT 16 "a_im";
    .port_info 2 /INPUT 16 "b_re";
    .port_info 3 /INPUT 16 "b_im";
    .port_info 4 /OUTPUT 16 "p_re";
    .port_info 5 /OUTPUT 16 "p_im";
P_0000014373e02b10 .param/l "FRAC" 0 6 3, +C4<00000000000000000000000000001011>;
P_0000014373e02b48 .param/l "MAX_VAL" 1 6 28, +C4<0111111111111111>;
P_0000014373e02b80 .param/l "MIN_VAL" 1 6 29, +C4<1000000000000000>;
P_0000014373e02bb8 .param/l "WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
v000001437439c4f0_0 .net/s *"_ivl_0", 31 0, L_0000014374402980;  1 drivers
v000001437439b190_0 .net/s *"_ivl_12", 31 0, L_0000014374401260;  1 drivers
v000001437439bd70_0 .net/s *"_ivl_14", 31 0, L_0000014374402a20;  1 drivers
v000001437439a970_0 .net/s *"_ivl_18", 31 0, L_0000014374401bc0;  1 drivers
v000001437439ad30_0 .net/s *"_ivl_2", 31 0, L_0000014374402160;  1 drivers
v000001437439add0_0 .net/s *"_ivl_20", 31 0, L_0000014374402340;  1 drivers
v000001437439bcd0_0 .net/s *"_ivl_24", 32 0, L_00000143744031a0;  1 drivers
v000001437439aab0_0 .net/s *"_ivl_26", 32 0, L_0000014374401940;  1 drivers
v000001437439b050_0 .net/s *"_ivl_30", 32 0, L_00000143744036a0;  1 drivers
v000001437439ab50_0 .net/s *"_ivl_32", 32 0, L_00000143744032e0;  1 drivers
v000001437439abf0_0 .net *"_ivl_38", 21 0, L_0000014374401d00;  1 drivers
v000001437439b2d0_0 .net *"_ivl_42", 21 0, L_0000014374403240;  1 drivers
v000001437439be10_0 .net/s *"_ivl_6", 31 0, L_0000014374403380;  1 drivers
v000001437439c270_0 .net/s *"_ivl_8", 31 0, L_00000143744016c0;  1 drivers
v000001437439bf50_0 .net/s "a_im", 15 0, v00000143743a3c40_0;  alias, 1 drivers
v000001437439bff0_0 .net/s "a_re", 15 0, v00000143743a3880_0;  alias, 1 drivers
v000001437439c090_0 .net/s "ac", 31 0, L_00000143744011c0;  1 drivers
v000001437439f8d0_0 .net/s "ad", 31 0, L_00000143744025c0;  1 drivers
v000001437439ecf0_0 .net/s "b_im", 15 0, v00000143743983f0_0;  alias, 1 drivers
v000001437439ddf0_0 .net/s "b_re", 15 0, v0000014374399390_0;  alias, 1 drivers
v000001437439dcb0_0 .net/s "bc", 31 0, L_0000014374401c60;  1 drivers
v000001437439f510_0 .net/s "bd", 31 0, L_0000014374401620;  1 drivers
v000001437439eed0_0 .net/s "im_long", 32 0, L_0000014374403740;  1 drivers
v000001437439f150_0 .net/s "im_shifted", 32 0, L_0000014374403420;  1 drivers
v000001437439da30_0 .var/s "p_im", 15 0;
v000001437439ed90_0 .var/s "p_re", 15 0;
v000001437439ef70_0 .net/s "re_long", 32 0, L_0000014374402b60;  1 drivers
v000001437439d170_0 .net/s "re_shifted", 32 0, L_0000014374401e40;  1 drivers
E_00000143742d7d50 .event anyedge, v000001437439d170_0, v000001437439f150_0;
L_0000014374402980 .extend/s 32, v00000143743a3880_0;
L_0000014374402160 .extend/s 32, v0000014374399390_0;
L_00000143744011c0 .arith/mult 32, L_0000014374402980, L_0000014374402160;
L_0000014374403380 .extend/s 32, v00000143743a3c40_0;
L_00000143744016c0 .extend/s 32, v00000143743983f0_0;
L_0000014374401620 .arith/mult 32, L_0000014374403380, L_00000143744016c0;
L_0000014374401260 .extend/s 32, v00000143743a3880_0;
L_0000014374402a20 .extend/s 32, v00000143743983f0_0;
L_00000143744025c0 .arith/mult 32, L_0000014374401260, L_0000014374402a20;
L_0000014374401bc0 .extend/s 32, v00000143743a3c40_0;
L_0000014374402340 .extend/s 32, v0000014374399390_0;
L_0000014374401c60 .arith/mult 32, L_0000014374401bc0, L_0000014374402340;
L_00000143744031a0 .extend/s 33, L_00000143744011c0;
L_0000014374401940 .extend/s 33, L_0000014374401620;
L_0000014374402b60 .arith/sub 33, L_00000143744031a0, L_0000014374401940;
L_00000143744036a0 .extend/s 33, L_00000143744025c0;
L_00000143744032e0 .extend/s 33, L_0000014374401c60;
L_0000014374403740 .arith/sum 33, L_00000143744036a0, L_00000143744032e0;
L_0000014374401d00 .part L_0000014374402b60, 11, 22;
L_0000014374401e40 .extend/s 33, L_0000014374401d00;
L_0000014374403240 .part L_0000014374403740, 11, 22;
L_0000014374403420 .extend/s 33, L_0000014374403240;
    .scope S_000001437438e450;
T_15 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v00000143743943e0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_15.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v00000143743951a0_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374394980_0, 0;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v0000014374395060_0, 0;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v0000014374396320_0, 0;
    %pushi/vec4 0, 0, 48;
    %assign/vec4 v0000014374394840_0, 0;
    %pushi/vec4 0, 0, 48;
    %assign/vec4 v0000014374395240_0, 0;
    %pushi/vec4 0, 0, 96;
    %assign/vec4 v00000143743948e0_0, 0;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v00000143743957e0_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v00000143743959c0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374396500_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743947a0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374396820_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374394200_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743963c0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374395100_0, 0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743945c0_0, 0, 32;
T_15.2 ;
    %load/vec4 v00000143743945c0_0;
    %pad/s 67;
    %cmpi/s 16, 0, 67;
    %flag_or 5, 4;
    %jmp/0xz T_15.3, 5;
    %pushi/vec4 0, 0, 96;
    %ix/getv/s 3, v00000143743945c0_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395380, 0, 4;
    %load/vec4 v00000143743945c0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743945c0_0, 0, 32;
    %jmp T_15.2;
T_15.3 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743945c0_0, 0, 32;
T_15.4 ;
    %load/vec4 v00000143743945c0_0;
    %pad/s 65;
    %cmpi/s 96, 0, 65;
    %jmp/0xz T_15.5, 5;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v00000143743945c0_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395a60, 0, 4;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v00000143743945c0_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395e20, 0, 4;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v00000143743945c0_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374394660, 0, 4;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v00000143743945c0_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743966e0, 0, 4;
    %load/vec4 v00000143743945c0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743945c0_0, 0, 32;
    %jmp T_15.4;
T_15.5 ;
    %jmp T_15.1;
T_15.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374396500_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743947a0_0, 0;
    %load/vec4 v00000143743951a0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 3;
    %cmp/u;
    %jmp/1 T_15.6, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 3;
    %cmp/u;
    %jmp/1 T_15.7, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 3;
    %cmp/u;
    %jmp/1 T_15.8, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 3;
    %cmp/u;
    %jmp/1 T_15.9, 6;
    %jmp T_15.10;
T_15.6 ;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374394980_0, 0;
    %load/vec4 v00000143743960a0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_15.11, 8;
    %load/vec4 v0000014374395f60_0;
    %ix/load 3, 16, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395a60, 0, 4;
    %load/vec4 v0000014374394700_0;
    %ix/load 3, 16, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395e20, 0, 4;
    %load/vec4 v0000014374396000_0;
    %ix/load 3, 16, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374394660, 0, 4;
    %load/vec4 v0000014374394ac0_0;
    %ix/load 3, 16, 0;
    %flag_set/imm 4, 0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743966e0, 0, 4;
    %pushi/vec4 1, 0, 7;
    %assign/vec4 v0000014374394980_0, 0;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v00000143743951a0_0, 0;
T_15.11 ;
    %jmp T_15.10;
T_15.7 ;
    %load/vec4 v00000143743960a0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_15.13, 8;
    %load/vec4 v0000014374395f60_0;
    %load/vec4 v0000014374394980_0;
    %pad/u 32;
    %addi 16, 0, 32;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395a60, 0, 4;
    %load/vec4 v0000014374394700_0;
    %load/vec4 v0000014374394980_0;
    %pad/u 32;
    %addi 16, 0, 32;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395e20, 0, 4;
    %load/vec4 v0000014374396000_0;
    %load/vec4 v0000014374394980_0;
    %pad/u 32;
    %addi 16, 0, 32;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374394660, 0, 4;
    %load/vec4 v0000014374394ac0_0;
    %load/vec4 v0000014374394980_0;
    %pad/u 32;
    %addi 16, 0, 32;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743966e0, 0, 4;
    %load/vec4 v0000014374394980_0;
    %pad/u 33;
    %cmpi/e 79, 0, 33;
    %jmp/0xz  T_15.15, 4;
    %pushi/vec4 2, 0, 3;
    %assign/vec4 v00000143743951a0_0, 0;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v0000014374395060_0, 0;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v0000014374396320_0, 0;
    %pushi/vec4 0, 0, 48;
    %assign/vec4 v0000014374394840_0, 0;
    %pushi/vec4 0, 0, 48;
    %assign/vec4 v0000014374395240_0, 0;
    %pushi/vec4 0, 0, 96;
    %assign/vec4 v00000143743948e0_0, 0;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v00000143743957e0_0, 0;
T_15.15 ;
    %load/vec4 v0000014374394980_0;
    %addi 1, 0, 7;
    %assign/vec4 v0000014374394980_0, 0;
T_15.13 ;
    %jmp T_15.10;
T_15.8 ;
    %load/vec4 v0000014374395b00_0;
    %assign/vec4 v0000014374394840_0, 0;
    %load/vec4 v0000014374394480_0;
    %assign/vec4 v0000014374395240_0, 0;
    %load/vec4 v0000014374396320_0;
    %pad/u 32;
    %cmpi/e 15, 0, 32;
    %jmp/0xz  T_15.17, 4;
    %load/vec4 v0000014374395060_0;
    %pad/u 6;
    %ix/vec4 4;
    %load/vec4a v0000014374395380, 4;
    %pad/u 97;
    %load/vec4 v0000014374395560_0;
    %ix/load 4, 4, 0;
    %flag_set/imm 4, 0;
    %shiftr 4;
    %add;
    %pad/u 96;
    %load/vec4 v0000014374395060_0;
    %pad/u 6;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374395380, 0, 4;
    %load/vec4 v00000143743948e0_0;
    %load/vec4 v00000143743961e0_0;
    %cmp/u;
    %jmp/0xz  T_15.19, 5;
    %load/vec4 v00000143743961e0_0;
    %assign/vec4 v00000143743948e0_0, 0;
    %load/vec4 v0000014374395060_0;
    %assign/vec4 v00000143743957e0_0, 0;
T_15.19 ;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v0000014374396320_0, 0;
    %pushi/vec4 0, 0, 48;
    %assign/vec4 v0000014374394840_0, 0;
    %pushi/vec4 0, 0, 48;
    %assign/vec4 v0000014374395240_0, 0;
    %load/vec4 v0000014374395060_0;
    %pad/u 67;
    %cmpi/e 16, 0, 67;
    %jmp/0xz  T_15.21, 4;
    %pushi/vec4 3, 0, 3;
    %assign/vec4 v00000143743951a0_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v00000143743959c0_0, 0;
    %jmp T_15.22;
T_15.21 ;
    %load/vec4 v0000014374395060_0;
    %addi 1, 0, 5;
    %assign/vec4 v0000014374395060_0, 0;
T_15.22 ;
    %jmp T_15.18;
T_15.17 ;
    %load/vec4 v0000014374396320_0;
    %addi 1, 0, 5;
    %assign/vec4 v0000014374396320_0, 0;
T_15.18 ;
    %jmp T_15.10;
T_15.9 ;
    %load/vec4 v00000143743959c0_0;
    %pad/u 33;
    %cmpi/u 80, 0, 33;
    %jmp/0xz  T_15.23, 5;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374396500_0, 0;
    %load/vec4 v00000143743959c0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_15.25, 4;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v00000143743947a0_0, 0;
T_15.25 ;
    %load/vec4 v00000143743957e0_0;
    %pad/u 7;
    %load/vec4 v00000143743959c0_0;
    %add;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v0000014374395a60, 4;
    %assign/vec4 v0000014374396820_0, 0;
    %load/vec4 v00000143743957e0_0;
    %pad/u 7;
    %load/vec4 v00000143743959c0_0;
    %add;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v0000014374395e20, 4;
    %assign/vec4 v0000014374394200_0, 0;
    %load/vec4 v00000143743957e0_0;
    %pad/u 7;
    %load/vec4 v00000143743959c0_0;
    %add;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v0000014374394660, 4;
    %assign/vec4 v00000143743963c0_0, 0;
    %load/vec4 v00000143743957e0_0;
    %pad/u 7;
    %load/vec4 v00000143743959c0_0;
    %add;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v00000143743966e0, 4;
    %assign/vec4 v0000014374395100_0, 0;
    %load/vec4 v00000143743959c0_0;
    %addi 1, 0, 7;
    %assign/vec4 v00000143743959c0_0, 0;
    %jmp T_15.24;
T_15.23 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374396500_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v00000143743951a0_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374394980_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v00000143743959c0_0, 0;
T_15.24 ;
    %jmp T_15.10;
T_15.10 ;
    %pop/vec4 1;
T_15.1 ;
    %jmp T_15;
    .thread T_15;
    .scope S_000001437438e450;
T_16 ;
    %wait E_00000143742d1690;
    %load/vec4 v00000143743947a0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_16.0, 8;
    %vpi_call/w 14 197 "$display", "[DBG][SYNC] best_idx=%0d T=%t", v00000143743957e0_0, $time {0 0 0};
T_16.0 ;
    %jmp T_16;
    .thread T_16;
    .scope S_0000014374322960;
T_17 ;
    %wait E_00000143742d7190;
    %load/vec4 v00000143742e51d0_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_17.0, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v00000143742e4eb0_0, 0, 16;
    %jmp T_17.1;
T_17.0 ;
    %load/vec4 v00000143742e51d0_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_17.2, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v00000143742e4eb0_0, 0, 16;
    %jmp T_17.3;
T_17.2 ;
    %load/vec4 v00000143742e51d0_0;
    %parti/s 16, 0, 2;
    %store/vec4 v00000143742e4eb0_0, 0, 16;
T_17.3 ;
T_17.1 ;
    %load/vec4 v00000143742e5d10_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_17.4, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v00000143742e4e10_0, 0, 16;
    %jmp T_17.5;
T_17.4 ;
    %load/vec4 v00000143742e5d10_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_17.6, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v00000143742e4e10_0, 0, 16;
    %jmp T_17.7;
T_17.6 ;
    %load/vec4 v00000143742e5d10_0;
    %parti/s 16, 0, 2;
    %store/vec4 v00000143742e4e10_0, 0, 16;
T_17.7 ;
T_17.5 ;
    %jmp T_17;
    .thread T_17, $push;
    .scope S_00000143743235e0;
T_18 ;
    %wait E_00000143742d75d0;
    %load/vec4 v0000014374344ba0_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_18.0, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v0000014374344d80_0, 0, 16;
    %jmp T_18.1;
T_18.0 ;
    %load/vec4 v0000014374344ba0_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_18.2, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v0000014374344d80_0, 0, 16;
    %jmp T_18.3;
T_18.2 ;
    %load/vec4 v0000014374344ba0_0;
    %parti/s 16, 0, 2;
    %store/vec4 v0000014374344d80_0, 0, 16;
T_18.3 ;
T_18.1 ;
    %load/vec4 v00000143742b8a50_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_18.4, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v00000143743447e0_0, 0, 16;
    %jmp T_18.5;
T_18.4 ;
    %load/vec4 v00000143742b8a50_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_18.6, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v00000143743447e0_0, 0, 16;
    %jmp T_18.7;
T_18.6 ;
    %load/vec4 v00000143742b8a50_0;
    %parti/s 16, 0, 2;
    %store/vec4 v00000143743447e0_0, 0, 16;
T_18.7 ;
T_18.5 ;
    %jmp T_18;
    .thread T_18, $push;
    .scope S_0000014374322af0;
T_19 ;
    %wait E_00000143742d7210;
    %load/vec4 v0000014374344b00_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %jmp/0xz  T_19.0, 5;
    %load/vec4 v0000014374344b00_0;
    %inv;
    %pushi/vec4 1, 0, 16;
    %add;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374343ca0, 4, 0;
    %load/vec4 v0000014374344ce0_0;
    %inv;
    %pushi/vec4 1, 0, 16;
    %add;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374344f60, 4, 0;
    %pushi/vec4 6434, 0, 16;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v00000143743442e0, 4, 0;
    %jmp T_19.1;
T_19.0 ;
    %load/vec4 v0000014374344b00_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374343ca0, 4, 0;
    %load/vec4 v0000014374344ce0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374344f60, 4, 0;
    %pushi/vec4 0, 0, 16;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v00000143743442e0, 4, 0;
T_19.1 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743438e0_0, 0, 32;
T_19.2 ;
    %load/vec4 v00000143743438e0_0;
    %cmpi/s 12, 0, 32;
    %jmp/0xz T_19.3, 5;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374344f60, 4;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_19.4, 5;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374343ca0, 4;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374344f60, 4;
    %load/vec4 v00000143743438e0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v00000143743438e0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374343ca0, 4, 0;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374344f60, 4;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374343ca0, 4;
    %load/vec4 v00000143743438e0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v00000143743438e0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374344f60, 4, 0;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v00000143743442e0, 4;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374343c00, 4;
    %add;
    %load/vec4 v00000143743438e0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743442e0, 4, 0;
    %jmp T_19.5;
T_19.4 ;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374343ca0, 4;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374344f60, 4;
    %load/vec4 v00000143743438e0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v00000143743438e0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374343ca0, 4, 0;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374344f60, 4;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374343ca0, 4;
    %load/vec4 v00000143743438e0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v00000143743438e0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374344f60, 4, 0;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v00000143743442e0, 4;
    %ix/getv/s 4, v00000143743438e0_0;
    %load/vec4a v0000014374343c00, 4;
    %sub;
    %load/vec4 v00000143743438e0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743442e0, 4, 0;
T_19.5 ;
    %load/vec4 v00000143743438e0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743438e0_0, 0, 32;
    %jmp T_19.2;
T_19.3 ;
    %ix/load 4, 12, 0;
    %flag_set/imm 4, 0;
    %load/vec4a v00000143743442e0, 4;
    %store/vec4 v0000014374345320_0, 0, 16;
    %jmp T_19;
    .thread T_19, $push;
    .scope S_0000014374322e10;
T_20 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v0000014374381260_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_20.0, 8;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v00000143743819e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374381940_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374344600_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374343840_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374344060_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374343a20_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743450a0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374345000_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743444c0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374344420_0, 0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374381800_0, 0, 32;
T_20.2 ;
    %load/vec4 v0000014374381800_0;
    %cmpi/s 64, 0, 32;
    %jmp/0xz T_20.3, 5;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v0000014374381800_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374344920, 0, 4;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v0000014374381800_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374344740, 0, 4;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v0000014374381800_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374380cc0, 0, 4;
    %pushi/vec4 0, 0, 16;
    %ix/getv/s 3, v0000014374381800_0;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743449c0, 0, 4;
    %load/vec4 v0000014374381800_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374381800_0, 0, 32;
    %jmp T_20.2;
T_20.3 ;
    %jmp T_20.1;
T_20.0 ;
    %load/vec4 v0000014374381620_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_20.4, 8;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v00000143743819e0_0, 0;
T_20.4 ;
    %load/vec4 v0000014374381760_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_20.6, 8;
    %load/vec4 v0000014374381e40_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v0000014374344920, 4;
    %assign/vec4 v0000014374344600_0, 0;
    %load/vec4 v0000014374381e40_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v0000014374344740, 4;
    %assign/vec4 v0000014374343840_0, 0;
    %load/vec4 v0000014374381e40_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v0000014374380cc0, 4;
    %assign/vec4 v0000014374344060_0, 0;
    %load/vec4 v0000014374381e40_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v00000143743449c0, 4;
    %assign/vec4 v0000014374343a20_0, 0;
    %load/vec4 v00000143743818a0_0;
    %load/vec4 v00000143743819e0_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374344920, 0, 4;
    %load/vec4 v00000143743816c0_0;
    %load/vec4 v00000143743819e0_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374344740, 0, 4;
    %load/vec4 v0000014374381300_0;
    %load/vec4 v00000143743819e0_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374380cc0, 0, 4;
    %load/vec4 v0000014374381f80_0;
    %load/vec4 v00000143743819e0_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743449c0, 0, 4;
    %load/vec4 v00000143743818a0_0;
    %assign/vec4 v00000143743450a0_0, 0;
    %load/vec4 v00000143743816c0_0;
    %assign/vec4 v0000014374345000_0, 0;
    %load/vec4 v0000014374381300_0;
    %assign/vec4 v00000143743444c0_0, 0;
    %load/vec4 v0000014374381f80_0;
    %assign/vec4 v0000014374344420_0, 0;
    %load/vec4 v00000143743819e0_0;
    %pad/u 32;
    %cmpi/e 63, 0, 32;
    %flag_mov 8, 4;
    %jmp/0 T_20.8, 8;
    %pushi/vec4 0, 0, 6;
    %jmp/1 T_20.9, 8;
T_20.8 ; End of true expr.
    %load/vec4 v00000143743819e0_0;
    %addi 1, 0, 6;
    %jmp/0 T_20.9, 8;
 ; End of false expr.
    %blend;
T_20.9;
    %assign/vec4 v00000143743819e0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374381940_0, 0;
    %jmp T_20.7;
T_20.6 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374381940_0, 0;
T_20.7 ;
T_20.1 ;
    %jmp T_20;
    .thread T_20;
    .scope S_0000014374322e10;
T_21 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v0000014374381260_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_21.0, 8;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000014374344560_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000014374345500_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374345140_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374380360_0, 0;
    %jmp T_21.1;
T_21.0 ;
    %load/vec4 v0000014374381620_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_21.2, 8;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000014374344560_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0000014374345500_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374345140_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374380360_0, 0;
    %jmp T_21.3;
T_21.2 ;
    %load/vec4 v0000014374381940_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_21.4, 8;
    %load/vec4 v0000014374380360_0;
    %pad/u 32;
    %cmpi/u 64, 0, 32;
    %flag_inv 5; GE is !LT
    %flag_get/vec4 5;
    %jmp/0 T_21.8, 5;
    %load/vec4 v0000014374380360_0;
    %pad/u 32;
    %cmpi/u 80, 0, 32;
    %flag_get/vec4 5;
    %and;
T_21.8;
    %flag_set/vec4 8;
    %jmp/0xz  T_21.6, 8;
    %load/vec4 v0000014374344560_0;
    %load/vec4 v0000014374380b80_0;
    %pad/s 32;
    %add;
    %assign/vec4 v0000014374344560_0, 0;
    %load/vec4 v0000014374345500_0;
    %load/vec4 v0000014374380c20_0;
    %pad/s 32;
    %add;
    %assign/vec4 v0000014374345500_0, 0;
    %load/vec4 v0000014374380360_0;
    %pad/u 32;
    %pushi/vec4 79, 0, 32;
    %cmp/e;
    %flag_get/vec4 4;
    %assign/vec4 v0000014374345140_0, 0;
    %jmp T_21.7;
T_21.6 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374345140_0, 0;
T_21.7 ;
    %load/vec4 v0000014374380360_0;
    %addi 1, 0, 7;
    %assign/vec4 v0000014374380360_0, 0;
    %jmp T_21.5;
T_21.4 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374345140_0, 0;
T_21.5 ;
T_21.3 ;
T_21.1 ;
    %jmp T_21;
    .thread T_21;
    .scope S_0000014374322e10;
T_22 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v0000014374381260_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_22.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374345460_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743451e0_0, 0;
    %jmp T_22.1;
T_22.0 ;
    %load/vec4 v0000014374345140_0;
    %assign/vec4 v0000014374345460_0, 0;
    %load/vec4 v00000143743441a0_0;
    %assign/vec4 v00000143743451e0_0, 0;
T_22.1 ;
    %jmp T_22;
    .thread T_22;
    .scope S_0000014374322e10;
T_23 ;
    %wait E_00000143742d1690;
    %load/vec4 v0000014374345140_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_23.0, 8;
    %vpi_call/w 5 220 "$display", "[DBG][CFO ] acc_re=%0d acc_im=%0d angle_out=%0d eps_hat=%0d", v0000014374344560_0, v0000014374345500_0, v0000014374343fc0_0, v00000143743441a0_0 {0 0 0};
T_23.0 ;
    %jmp T_23;
    .thread T_23;
    .scope S_00000143743820f0;
T_24 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437438b8f0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_24.0, 8;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437438b850_0, 0;
    %jmp T_24.1;
T_24.0 ;
    %load/vec4 v000001437438a310_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_24.2, 8;
    %load/vec4 v000001437438b170_0;
    %muli 201, 0, 16;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %assign/vec4 v000001437438b850_0, 0;
T_24.2 ;
T_24.1 ;
    %jmp T_24;
    .thread T_24;
    .scope S_00000143743820f0;
T_25 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437438b8f0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_25.0, 8;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437438a810_0, 0;
    %jmp T_25.1;
T_25.0 ;
    %load/vec4 v000001437438a810_0;
    %pad/s 17;
    %store/vec4 v000001437438b7b0_0, 0, 17;
    %load/vec4 v000001437438a310_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_25.2, 8;
    %pushi/vec4 0, 0, 17;
    %store/vec4 v000001437438b7b0_0, 0, 17;
T_25.2 ;
    %load/vec4 v000001437438a8b0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_25.4, 8;
    %load/vec4 v000001437438a810_0;
    %pad/s 17;
    %load/vec4 v000001437438b850_0;
    %pad/s 17;
    %sub;
    %store/vec4 v000001437438b7b0_0, 0, 17;
T_25.4 ;
    %load/vec4 v000001437438ba30_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_25.6, 8;
    %load/vec4 v000001437438b7b0_0;
    %load/vec4 v000001437438b0d0_0;
    %pad/s 17;
    %sub;
    %store/vec4 v000001437438b7b0_0, 0, 17;
T_25.6 ;
    %load/vec4 v000001437438b7b0_0;
    %cmpi/s 6434, 0, 17;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_25.8, 5;
    %load/vec4 v000001437438b7b0_0;
    %subi 12868, 0, 17;
    %pad/s 16;
    %assign/vec4 v000001437438a810_0, 0;
    %jmp T_25.9;
T_25.8 ;
    %load/vec4 v000001437438b7b0_0;
    %cmpi/s 124638, 0, 17;
    %jmp/0xz  T_25.10, 5;
    %load/vec4 v000001437438b7b0_0;
    %addi 12868, 0, 17;
    %pad/s 16;
    %assign/vec4 v000001437438a810_0, 0;
    %jmp T_25.11;
T_25.10 ;
    %load/vec4 v000001437438b7b0_0;
    %parti/s 16, 0, 2;
    %assign/vec4 v000001437438a810_0, 0;
T_25.11 ;
T_25.9 ;
T_25.1 ;
    %jmp T_25;
    .thread T_25;
    .scope S_00000143743820f0;
T_26 ;
    %wait E_00000143742d1690;
    %load/vec4 v000001437438a810_0;
    %assign/vec4 v000001437438bb70_0, 0;
    %jmp T_26;
    .thread T_26;
    .scope S_000001437438fa30;
T_27 ;
    %wait E_00000143742d7590;
    %load/vec4 v000001437438de70_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v000001437438df10, 4, 0;
    %load/vec4 v000001437438d5b0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v000001437438d010, 4, 0;
    %load/vec4 v000001437438bc10_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v000001437438c930, 4, 0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v000001437438a6d0_0, 0, 32;
T_27.0 ;
    %load/vec4 v000001437438a6d0_0;
    %cmpi/s 12, 0, 32;
    %jmp/0xz T_27.1, 5;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438c930, 4;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_inv 5; GE is !LT
    %jmp/0xz  T_27.2, 5;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438df10, 4;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438d010, 4;
    %load/vec4 v000001437438a6d0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v000001437438a6d0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438df10, 4, 0;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438d010, 4;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438df10, 4;
    %load/vec4 v000001437438a6d0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v000001437438a6d0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438d010, 4, 0;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438c930, 4;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438bad0, 4;
    %sub;
    %load/vec4 v000001437438a6d0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438c930, 4, 0;
    %jmp T_27.3;
T_27.2 ;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438df10, 4;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438d010, 4;
    %load/vec4 v000001437438a6d0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v000001437438a6d0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438df10, 4, 0;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438d010, 4;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438df10, 4;
    %load/vec4 v000001437438a6d0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v000001437438a6d0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438d010, 4, 0;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438c930, 4;
    %ix/getv/s 4, v000001437438a6d0_0;
    %load/vec4a v000001437438bad0, 4;
    %add;
    %load/vec4 v000001437438a6d0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438c930, 4, 0;
T_27.3 ;
    %load/vec4 v000001437438a6d0_0;
    %addi 1, 0, 32;
    %store/vec4 v000001437438a6d0_0, 0, 32;
    %jmp T_27.0;
T_27.1 ;
    %jmp T_27;
    .thread T_27, $push;
    .scope S_000001437438fa30;
T_28 ;
    %wait E_00000143742d7550;
    %load/vec4 v000001437438d8d0_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v000001437438dfb0_0, 0, 16;
    %load/vec4 v000001437438d290_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v000001437438d650_0, 0, 16;
    %jmp T_28;
    .thread T_28, $push;
    .scope S_000001437438ea90;
T_29 ;
    %wait E_00000143742d7610;
    %load/vec4 v000001437438cbb0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v000001437438d830, 4, 0;
    %load/vec4 v000001437438cb10_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v000001437438ca70, 4, 0;
    %load/vec4 v000001437438d0b0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v000001437438d470, 4, 0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v000001437438dbf0_0, 0, 32;
T_29.0 ;
    %load/vec4 v000001437438dbf0_0;
    %cmpi/s 12, 0, 32;
    %jmp/0xz T_29.1, 5;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d470, 4;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_inv 5; GE is !LT
    %jmp/0xz  T_29.2, 5;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d830, 4;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438ca70, 4;
    %load/vec4 v000001437438dbf0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v000001437438dbf0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438d830, 4, 0;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438ca70, 4;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d830, 4;
    %load/vec4 v000001437438dbf0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v000001437438dbf0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438ca70, 4, 0;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d470, 4;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d6f0, 4;
    %sub;
    %load/vec4 v000001437438dbf0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438d470, 4, 0;
    %jmp T_29.3;
T_29.2 ;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d830, 4;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438ca70, 4;
    %load/vec4 v000001437438dbf0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v000001437438dbf0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438d830, 4, 0;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438ca70, 4;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d830, 4;
    %load/vec4 v000001437438dbf0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v000001437438dbf0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438ca70, 4, 0;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d470, 4;
    %ix/getv/s 4, v000001437438dbf0_0;
    %load/vec4a v000001437438d6f0, 4;
    %add;
    %load/vec4 v000001437438dbf0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v000001437438d470, 4, 0;
T_29.3 ;
    %load/vec4 v000001437438dbf0_0;
    %addi 1, 0, 32;
    %store/vec4 v000001437438dbf0_0, 0, 32;
    %jmp T_29.0;
T_29.1 ;
    %jmp T_29;
    .thread T_29, $push;
    .scope S_000001437438ea90;
T_30 ;
    %wait E_00000143742d6fd0;
    %load/vec4 v000001437438d510_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v000001437438dc90_0, 0, 16;
    %load/vec4 v000001437438d330_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v000001437438cc50_0, 0, 16;
    %jmp T_30;
    .thread T_30, $push;
    .scope S_000001437438ef40;
T_31 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v0000014374390470_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_31.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374390970_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437438dd30_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437438d150_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437438d1f0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437438db50_0, 0;
    %jmp T_31.1;
T_31.0 ;
    %load/vec4 v000001437438dab0_0;
    %assign/vec4 v0000014374390970_0, 0;
    %load/vec4 v0000014374390fb0_0;
    %assign/vec4 v000001437438dd30_0, 0;
    %load/vec4 v00000143743910f0_0;
    %assign/vec4 v000001437438d150_0, 0;
    %load/vec4 v0000014374392450_0;
    %assign/vec4 v000001437438d1f0_0, 0;
    %load/vec4 v0000014374392630_0;
    %assign/vec4 v000001437438db50_0, 0;
T_31.1 ;
    %jmp T_31;
    .thread T_31;
    .scope S_0000014374382a50;
T_32 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v0000014374388f60_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_32.0, 8;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374389a00_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374389780_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374388ec0_0, 0;
    %jmp T_32.1;
T_32.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374388ec0_0, 0;
    %load/vec4 v00000143743898c0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_32.2, 8;
    %load/vec4 v00000143743896e0_0;
    %load/vec4 v0000014374389780_0;
    %load/vec4 v0000014374389a00_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743889c0, 0, 4;
    %load/vec4 v0000014374389320_0;
    %load/vec4 v0000014374389780_0;
    %load/vec4 v0000014374389a00_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374389aa0, 0, 4;
    %load/vec4 v0000014374389a00_0;
    %pad/u 32;
    %cmpi/e 63, 0, 32;
    %jmp/0xz  T_32.4, 4;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374389a00_0, 0;
    %load/vec4 v0000014374389780_0;
    %inv;
    %assign/vec4 v0000014374389780_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374388ec0_0, 0;
    %jmp T_32.5;
T_32.4 ;
    %load/vec4 v0000014374389a00_0;
    %addi 1, 0, 7;
    %assign/vec4 v0000014374389a00_0, 0;
T_32.5 ;
T_32.2 ;
T_32.1 ;
    %jmp T_32;
    .thread T_32;
    .scope S_0000014374382a50;
T_33 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v0000014374388f60_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_33.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374389fa0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374389b40_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374389dc0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374389d20_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374389c80_0, 0;
    %jmp T_33.1;
T_33.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374389b40_0, 0;
    %load/vec4 v0000014374389dc0_0;
    %pad/u 32;
    %cmpi/ne 0, 0, 32;
    %jmp/0xz  T_33.2, 4;
    %load/vec4 v0000014374389dc0_0;
    %subi 1, 0, 7;
    %assign/vec4 v0000014374389dc0_0, 0;
T_33.2 ;
    %load/vec4 v0000014374389dc0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %flag_get/vec4 4;
    %jmp/0 T_33.6, 4;
    %load/vec4 v0000014374389d20_0;
    %and;
T_33.6;
    %flag_set/vec4 8;
    %jmp/0xz  T_33.4, 8;
    %load/vec4 v0000014374389c80_0;
    %assign/vec4 v0000014374389fa0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374389b40_0, 0;
    %pushi/vec4 64, 0, 7;
    %assign/vec4 v0000014374389dc0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374389d20_0, 0;
T_33.4 ;
    %load/vec4 v0000014374388ec0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_33.7, 8;
    %load/vec4 v0000014374389dc0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %flag_get/vec4 4;
    %jmp/0 T_33.11, 4;
    %load/vec4 v0000014374389d20_0;
    %nor/r;
    %and;
T_33.11;
    %flag_set/vec4 8;
    %jmp/0xz  T_33.9, 8;
    %load/vec4 v0000014374389780_0;
    %inv;
    %assign/vec4 v0000014374389fa0_0, 0;
    %alloc S_0000014374383090;
    %load/vec4 v0000014374389780_0;
    %inv;
    %store/vec4 v0000014374386800_0, 0, 1;
    %fork TD_tb_top_receiver.u_top.u_fft1.run_fft, S_0000014374383090;
    %join;
    %free S_0000014374383090;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374389b40_0, 0;
    %pushi/vec4 64, 0, 7;
    %assign/vec4 v0000014374389dc0_0, 0;
    %jmp T_33.10;
T_33.9 ;
    %load/vec4 v0000014374389d20_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_33.12, 8;
    %load/vec4 v0000014374389780_0;
    %inv;
    %assign/vec4 v0000014374389c80_0, 0;
    %alloc S_0000014374383090;
    %load/vec4 v0000014374389780_0;
    %inv;
    %store/vec4 v0000014374386800_0, 0, 1;
    %fork TD_tb_top_receiver.u_top.u_fft1.run_fft, S_0000014374383090;
    %join;
    %free S_0000014374383090;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374389d20_0, 0;
T_33.12 ;
T_33.10 ;
T_33.7 ;
T_33.1 ;
    %jmp T_33;
    .thread T_33;
    .scope S_0000014374382730;
T_34 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437438b670_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_34.0, 8;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437438ad10_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438a630_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438b5d0_0, 0;
    %jmp T_34.1;
T_34.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438b5d0_0, 0;
    %load/vec4 v000001437438c070_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_34.2, 8;
    %load/vec4 v000001437438ac70_0;
    %load/vec4 v000001437438a630_0;
    %load/vec4 v000001437438ad10_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437438ae50, 0, 4;
    %load/vec4 v000001437438bf30_0;
    %load/vec4 v000001437438a630_0;
    %load/vec4 v000001437438ad10_0;
    %parti/s 6, 0, 2;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437438c110, 0, 4;
    %load/vec4 v000001437438ad10_0;
    %pad/u 32;
    %cmpi/e 63, 0, 32;
    %jmp/0xz  T_34.4, 4;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437438ad10_0, 0;
    %load/vec4 v000001437438a630_0;
    %inv;
    %assign/vec4 v000001437438a630_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001437438b5d0_0, 0;
    %jmp T_34.5;
T_34.4 ;
    %load/vec4 v000001437438ad10_0;
    %addi 1, 0, 7;
    %assign/vec4 v000001437438ad10_0, 0;
T_34.5 ;
T_34.2 ;
T_34.1 ;
    %jmp T_34;
    .thread T_34;
    .scope S_0000014374382730;
T_35 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437438b670_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_35.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438b530_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438a450_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437438c2f0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438a270_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438c1b0_0, 0;
    %jmp T_35.1;
T_35.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438a450_0, 0;
    %load/vec4 v000001437438c2f0_0;
    %pad/u 32;
    %cmpi/ne 0, 0, 32;
    %jmp/0xz  T_35.2, 4;
    %load/vec4 v000001437438c2f0_0;
    %subi 1, 0, 7;
    %assign/vec4 v000001437438c2f0_0, 0;
T_35.2 ;
    %load/vec4 v000001437438c2f0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %flag_get/vec4 4;
    %jmp/0 T_35.6, 4;
    %load/vec4 v000001437438a270_0;
    %and;
T_35.6;
    %flag_set/vec4 8;
    %jmp/0xz  T_35.4, 8;
    %load/vec4 v000001437438c1b0_0;
    %assign/vec4 v000001437438b530_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001437438a450_0, 0;
    %pushi/vec4 64, 0, 7;
    %assign/vec4 v000001437438c2f0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437438a270_0, 0;
T_35.4 ;
    %load/vec4 v000001437438b5d0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_35.7, 8;
    %load/vec4 v000001437438c2f0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %flag_get/vec4 4;
    %jmp/0 T_35.11, 4;
    %load/vec4 v000001437438a270_0;
    %nor/r;
    %and;
T_35.11;
    %flag_set/vec4 8;
    %jmp/0xz  T_35.9, 8;
    %load/vec4 v000001437438a630_0;
    %inv;
    %assign/vec4 v000001437438b530_0, 0;
    %alloc S_00000143743839f0;
    %load/vec4 v000001437438a630_0;
    %inv;
    %store/vec4 v000001437438ab30_0, 0, 1;
    %fork TD_tb_top_receiver.u_top.u_fft2.run_fft, S_00000143743839f0;
    %join;
    %free S_00000143743839f0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001437438a450_0, 0;
    %pushi/vec4 64, 0, 7;
    %assign/vec4 v000001437438c2f0_0, 0;
    %jmp T_35.10;
T_35.9 ;
    %load/vec4 v000001437438a270_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_35.12, 8;
    %load/vec4 v000001437438a630_0;
    %inv;
    %assign/vec4 v000001437438c1b0_0, 0;
    %alloc S_00000143743839f0;
    %load/vec4 v000001437438a630_0;
    %inv;
    %store/vec4 v000001437438ab30_0, 0, 1;
    %fork TD_tb_top_receiver.u_top.u_fft2.run_fft, S_00000143743839f0;
    %join;
    %free S_00000143743839f0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001437438a270_0, 0;
T_35.12 ;
T_35.10 ;
T_35.7 ;
T_35.1 ;
    %jmp T_35;
    .thread T_35;
    .scope S_000001437438e900;
T_36 ;
    %wait E_00000143742d76d0;
    %load/vec4 v0000014374397d60_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_36.0, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v00000143743975e0_0, 0, 16;
    %jmp T_36.1;
T_36.0 ;
    %load/vec4 v0000014374397d60_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_36.2, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v00000143743975e0_0, 0, 16;
    %jmp T_36.3;
T_36.2 ;
    %load/vec4 v0000014374397d60_0;
    %parti/s 16, 0, 2;
    %store/vec4 v00000143743975e0_0, 0, 16;
T_36.3 ;
T_36.1 ;
    %load/vec4 v00000143743974a0_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_36.4, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v0000014374396be0_0, 0, 16;
    %jmp T_36.5;
T_36.4 ;
    %load/vec4 v00000143743974a0_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_36.6, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v0000014374396be0_0, 0, 16;
    %jmp T_36.7;
T_36.6 ;
    %load/vec4 v00000143743974a0_0;
    %parti/s 16, 0, 2;
    %store/vec4 v0000014374396be0_0, 0, 16;
T_36.7 ;
T_36.5 ;
    %jmp T_36;
    .thread T_36, $push;
    .scope S_000001437438e130;
T_37 ;
    %wait E_00000143742d7650;
    %load/vec4 v000001437439c450_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_37.0, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v000001437439b4b0_0, 0, 16;
    %jmp T_37.1;
T_37.0 ;
    %load/vec4 v000001437439c450_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_37.2, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v000001437439b4b0_0, 0, 16;
    %jmp T_37.3;
T_37.2 ;
    %load/vec4 v000001437439c450_0;
    %parti/s 16, 0, 2;
    %store/vec4 v000001437439b4b0_0, 0, 16;
T_37.3 ;
T_37.1 ;
    %load/vec4 v000001437439c950_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_37.4, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v000001437439b9b0_0, 0, 16;
    %jmp T_37.5;
T_37.4 ;
    %load/vec4 v000001437439c950_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_37.6, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v000001437439b9b0_0, 0, 16;
    %jmp T_37.7;
T_37.6 ;
    %load/vec4 v000001437439c950_0;
    %parti/s 16, 0, 2;
    %store/vec4 v000001437439b9b0_0, 0, 16;
T_37.7 ;
T_37.5 ;
    %jmp T_37;
    .thread T_37, $push;
    .scope S_000001437438fd50;
T_38 ;
    %wait E_00000143742d8190;
    %load/vec4 v000001437439aa10_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_38.0, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v000001437439baf0_0, 0, 16;
    %jmp T_38.1;
T_38.0 ;
    %load/vec4 v000001437439aa10_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_38.2, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v000001437439baf0_0, 0, 16;
    %jmp T_38.3;
T_38.2 ;
    %load/vec4 v000001437439aa10_0;
    %parti/s 16, 0, 2;
    %store/vec4 v000001437439baf0_0, 0, 16;
T_38.3 ;
T_38.1 ;
    %load/vec4 v000001437439afb0_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_38.4, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v000001437439d0d0_0, 0, 16;
    %jmp T_38.5;
T_38.4 ;
    %load/vec4 v000001437439afb0_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_38.6, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v000001437439d0d0_0, 0, 16;
    %jmp T_38.7;
T_38.6 ;
    %load/vec4 v000001437439afb0_0;
    %parti/s 16, 0, 2;
    %store/vec4 v000001437439d0d0_0, 0, 16;
T_38.7 ;
T_38.5 ;
    %jmp T_38;
    .thread T_38, $push;
    .scope S_000001437438ec20;
T_39 ;
    %wait E_00000143742d7d50;
    %load/vec4 v000001437439d170_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_39.0, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v000001437439ed90_0, 0, 16;
    %jmp T_39.1;
T_39.0 ;
    %load/vec4 v000001437439d170_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_39.2, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v000001437439ed90_0, 0, 16;
    %jmp T_39.3;
T_39.2 ;
    %load/vec4 v000001437439d170_0;
    %parti/s 16, 0, 2;
    %store/vec4 v000001437439ed90_0, 0, 16;
T_39.3 ;
T_39.1 ;
    %load/vec4 v000001437439f150_0;
    %cmpi/s 32767, 0, 33;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_39.4, 5;
    %pushi/vec4 32767, 0, 16;
    %store/vec4 v000001437439da30_0, 0, 16;
    %jmp T_39.5;
T_39.4 ;
    %load/vec4 v000001437439f150_0;
    %pushi/vec4 4294950912, 0, 32;
    %concati/vec4 0, 0, 1;
    %cmp/s;
    %jmp/0xz  T_39.6, 5;
    %pushi/vec4 32768, 0, 16;
    %store/vec4 v000001437439da30_0, 0, 16;
    %jmp T_39.7;
T_39.6 ;
    %load/vec4 v000001437439f150_0;
    %parti/s 16, 0, 2;
    %store/vec4 v000001437439da30_0, 0, 16;
T_39.7 ;
T_39.5 ;
    %jmp T_39;
    .thread T_39, $push;
    .scope S_000001437438f260;
T_40 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437439f830_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_40.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437439db70_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439d210_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439f5b0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439ee30_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439d2b0_0, 0;
    %jmp T_40.1;
T_40.0 ;
    %load/vec4 v000001437439d8f0_0;
    %assign/vec4 v000001437439db70_0, 0;
    %load/vec4 v000001437439d8f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_40.2, 8;
    %load/vec4 v000001437439dc10_0;
    %load/vec4 v000001437439ebb0_0;
    %store/vec4 v00000143743954c0_0, 0, 16;
    %store/vec4 v0000014374394d40_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.u_top.u_zf.sat_add, S_000001437438e5e0;
    %assign/vec4 v000001437439d210_0, 0;
    %load/vec4 v000001437439e110_0;
    %load/vec4 v000001437439f6f0_0;
    %store/vec4 v00000143743954c0_0, 0, 16;
    %store/vec4 v0000014374394d40_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.u_top.u_zf.sat_add, S_000001437438e5e0;
    %assign/vec4 v000001437439f5b0_0, 0;
    %load/vec4 v000001437439f790_0;
    %load/vec4 v000001437439dfd0_0;
    %store/vec4 v00000143743954c0_0, 0, 16;
    %store/vec4 v0000014374394d40_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.u_top.u_zf.sat_add, S_000001437438e5e0;
    %assign/vec4 v000001437439ee30_0, 0;
    %load/vec4 v000001437439df30_0;
    %load/vec4 v000001437439d710_0;
    %store/vec4 v00000143743954c0_0, 0, 16;
    %store/vec4 v0000014374394d40_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.u_top.u_zf.sat_add, S_000001437438e5e0;
    %assign/vec4 v000001437439d2b0_0, 0;
    %jmp T_40.3;
T_40.2 ;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439d210_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439f5b0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439ee30_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439d2b0_0, 0;
T_40.3 ;
T_40.1 ;
    %jmp T_40;
    .thread T_40;
    .scope S_0000014374383860;
T_41 ;
    %wait E_00000143742d6cd0;
    %load/vec4 v00000143743853c0_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %jmp/0xz  T_41.0, 5;
    %load/vec4 v00000143743853c0_0;
    %inv;
    %pushi/vec4 1, 0, 16;
    %add;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374384d80, 4, 0;
    %load/vec4 v0000014374385780_0;
    %inv;
    %pushi/vec4 1, 0, 16;
    %add;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374385500, 4, 0;
    %pushi/vec4 6434, 0, 16;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374384e20, 4, 0;
    %jmp T_41.1;
T_41.0 ;
    %load/vec4 v00000143743853c0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374384d80, 4, 0;
    %load/vec4 v0000014374385780_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374385500, 4, 0;
    %pushi/vec4 0, 0, 16;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374384e20, 4, 0;
T_41.1 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374384600_0, 0, 32;
T_41.2 ;
    %load/vec4 v0000014374384600_0;
    %cmpi/s 12, 0, 32;
    %jmp/0xz T_41.3, 5;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374385500, 4;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_41.4, 5;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374384d80, 4;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374385500, 4;
    %load/vec4 v0000014374384600_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374384600_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384d80, 4, 0;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374385500, 4;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374384d80, 4;
    %load/vec4 v0000014374384600_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374384600_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374385500, 4, 0;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374384e20, 4;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v00000143743844c0, 4;
    %add;
    %load/vec4 v0000014374384600_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384e20, 4, 0;
    %jmp T_41.5;
T_41.4 ;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374384d80, 4;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374385500, 4;
    %load/vec4 v0000014374384600_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374384600_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384d80, 4, 0;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374385500, 4;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374384d80, 4;
    %load/vec4 v0000014374384600_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374384600_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374385500, 4, 0;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v0000014374384e20, 4;
    %ix/getv/s 4, v0000014374384600_0;
    %load/vec4a v00000143743844c0, 4;
    %sub;
    %load/vec4 v0000014374384600_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384e20, 4, 0;
T_41.5 ;
    %load/vec4 v0000014374384600_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374384600_0, 0, 32;
    %jmp T_41.2;
T_41.3 ;
    %ix/load 4, 12, 0;
    %flag_set/imm 4, 0;
    %load/vec4a v0000014374384e20, 4;
    %store/vec4 v0000014374385820_0, 0, 16;
    %jmp T_41;
    .thread T_41, $push;
    .scope S_0000014374382d70;
T_42 ;
    %wait E_00000143742d6f10;
    %load/vec4 v0000014374385f00_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %jmp/0xz  T_42.0, 5;
    %load/vec4 v0000014374385f00_0;
    %inv;
    %pushi/vec4 1, 0, 16;
    %add;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374384ec0, 4, 0;
    %load/vec4 v0000014374384560_0;
    %inv;
    %pushi/vec4 1, 0, 16;
    %add;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v00000143743855a0, 4, 0;
    %pushi/vec4 6434, 0, 16;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374385960, 4, 0;
    %jmp T_42.1;
T_42.0 ;
    %load/vec4 v0000014374385f00_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374384ec0, 4, 0;
    %load/vec4 v0000014374384560_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v00000143743855a0, 4, 0;
    %pushi/vec4 0, 0, 16;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374385960, 4, 0;
T_42.1 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374385280_0, 0, 32;
T_42.2 ;
    %load/vec4 v0000014374385280_0;
    %cmpi/s 12, 0, 32;
    %jmp/0xz T_42.3, 5;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v00000143743855a0, 4;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_or 5, 4; GT is !LE
    %flag_inv 5;
    %jmp/0xz  T_42.4, 5;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374384ec0, 4;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v00000143743855a0, 4;
    %load/vec4 v0000014374385280_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374385280_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384ec0, 4, 0;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v00000143743855a0, 4;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374384ec0, 4;
    %load/vec4 v0000014374385280_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374385280_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743855a0, 4, 0;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374385960, 4;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374384c40, 4;
    %add;
    %load/vec4 v0000014374385280_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374385960, 4, 0;
    %jmp T_42.5;
T_42.4 ;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374384ec0, 4;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v00000143743855a0, 4;
    %load/vec4 v0000014374385280_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374385280_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384ec0, 4, 0;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v00000143743855a0, 4;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374384ec0, 4;
    %load/vec4 v0000014374385280_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374385280_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743855a0, 4, 0;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374385960, 4;
    %ix/getv/s 4, v0000014374385280_0;
    %load/vec4a v0000014374384c40, 4;
    %sub;
    %load/vec4 v0000014374385280_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374385960, 4, 0;
T_42.5 ;
    %load/vec4 v0000014374385280_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374385280_0, 0, 32;
    %jmp T_42.2;
T_42.3 ;
    %ix/load 4, 12, 0;
    %flag_set/imm 4, 0;
    %load/vec4a v0000014374385960, 4;
    %store/vec4 v0000014374385640_0, 0, 16;
    %jmp T_42;
    .thread T_42, $push;
    .scope S_0000014374383d10;
T_43 ;
    %wait E_00000143742d7390;
    %load/vec4 v00000143743802c0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374380e00, 4, 0;
    %load/vec4 v0000014374380ea0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374380540, 4, 0;
    %load/vec4 v0000014374381c60_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v00000143743813a0, 4, 0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374381bc0_0, 0, 32;
T_43.0 ;
    %load/vec4 v0000014374381bc0_0;
    %cmpi/s 12, 0, 32;
    %jmp/0xz T_43.1, 5;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v00000143743813a0, 4;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_inv 5; GE is !LT
    %jmp/0xz  T_43.2, 5;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380e00, 4;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380540, 4;
    %load/vec4 v0000014374381bc0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374381bc0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374380e00, 4, 0;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380540, 4;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380e00, 4;
    %load/vec4 v0000014374381bc0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374381bc0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374380540, 4, 0;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v00000143743813a0, 4;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380400, 4;
    %sub;
    %load/vec4 v0000014374381bc0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743813a0, 4, 0;
    %jmp T_43.3;
T_43.2 ;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380e00, 4;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380540, 4;
    %load/vec4 v0000014374381bc0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374381bc0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374380e00, 4, 0;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380540, 4;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380e00, 4;
    %load/vec4 v0000014374381bc0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374381bc0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374380540, 4, 0;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v00000143743813a0, 4;
    %ix/getv/s 4, v0000014374381bc0_0;
    %load/vec4a v0000014374380400, 4;
    %add;
    %load/vec4 v0000014374381bc0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743813a0, 4, 0;
T_43.3 ;
    %load/vec4 v0000014374381bc0_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374381bc0_0, 0, 32;
    %jmp T_43.0;
T_43.1 ;
    %jmp T_43;
    .thread T_43, $push;
    .scope S_0000014374383d10;
T_44 ;
    %wait E_00000143742d6a90;
    %load/vec4 v00000143743811c0_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v00000143743804a0_0, 0, 16;
    %load/vec4 v0000014374380680_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v00000143743805e0_0, 0, 16;
    %jmp T_44;
    .thread T_44, $push;
    .scope S_00000143743836d0;
T_45 ;
    %wait E_00000143742d66d0;
    %load/vec4 v00000143743858c0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v00000143743814e0, 4, 0;
    %load/vec4 v0000014374384ce0_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374384100, 4, 0;
    %load/vec4 v0000014374381120_0;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0000014374385460, 4, 0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0000014374380ae0_0, 0, 32;
T_45.0 ;
    %load/vec4 v0000014374380ae0_0;
    %cmpi/s 12, 0, 32;
    %jmp/0xz T_45.1, 5;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374385460, 4;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_inv 5; GE is !LT
    %jmp/0xz  T_45.2, 5;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v00000143743814e0, 4;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374384100, 4;
    %load/vec4 v0000014374380ae0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374380ae0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743814e0, 4, 0;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374384100, 4;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v00000143743814e0, 4;
    %load/vec4 v0000014374380ae0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374380ae0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384100, 4, 0;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374385460, 4;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374380fe0, 4;
    %sub;
    %load/vec4 v0000014374380ae0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374385460, 4, 0;
    %jmp T_45.3;
T_45.2 ;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v00000143743814e0, 4;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374384100, 4;
    %load/vec4 v0000014374380ae0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %add;
    %load/vec4 v0000014374380ae0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v00000143743814e0, 4, 0;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374384100, 4;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v00000143743814e0, 4;
    %load/vec4 v0000014374380ae0_0;
    %ix/vec4 4;
    %shiftr/s 4;
    %sub;
    %load/vec4 v0000014374380ae0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374384100, 4, 0;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374385460, 4;
    %ix/getv/s 4, v0000014374380ae0_0;
    %load/vec4a v0000014374380fe0, 4;
    %add;
    %load/vec4 v0000014374380ae0_0;
    %addi 1, 0, 32;
    %ix/vec4/s 4;
    %store/vec4a v0000014374385460, 4, 0;
T_45.3 ;
    %load/vec4 v0000014374380ae0_0;
    %addi 1, 0, 32;
    %store/vec4 v0000014374380ae0_0, 0, 32;
    %jmp T_45.0;
T_45.1 ;
    %jmp T_45;
    .thread T_45, $push;
    .scope S_00000143743836d0;
T_46 ;
    %wait E_00000143742d6f90;
    %load/vec4 v0000014374384ba0_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v0000014374384b00_0, 0, 16;
    %load/vec4 v0000014374384a60_0;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %store/vec4 v0000014374385320_0, 0, 16;
    %jmp T_46;
    .thread T_46, $push;
    .scope S_0000014374322c80;
T_47 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v00000143743881a0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_47.0, 8;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v00000143743850a0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743841a0_0, 0;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v00000143743864e0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374384740_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743856e0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374385000_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374384420_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743869e0_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v0000014374387020_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374386a80_0, 0;
    %jmp T_47.1;
T_47.0 ;
    %load/vec4 v00000143743846a0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_47.2, 8;
    %load/vec4 v0000014374385a00_0;
    %load/vec4 v00000143743841a0_0;
    %load/vec4 v00000143743850a0_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374386f80, 0, 4;
    %load/vec4 v0000014374384380_0;
    %load/vec4 v00000143743841a0_0;
    %load/vec4 v00000143743850a0_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374387840, 0, 4;
    %load/vec4 v0000014374385be0_0;
    %load/vec4 v00000143743841a0_0;
    %load/vec4 v00000143743850a0_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v00000143743884c0, 0, 4;
    %load/vec4 v0000014374385140_0;
    %load/vec4 v00000143743841a0_0;
    %load/vec4 v00000143743850a0_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0000014374386760, 0, 4;
    %load/vec4 v00000143743850a0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_47.4, 4;
    %load/vec4 v0000014374384240_0;
    %pad/s 32;
    %assign/vec4 v00000143743864e0_0, 0;
    %load/vec4 v00000143743850a0_0;
    %addi 1, 0, 6;
    %assign/vec4 v00000143743850a0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374384740_0, 0;
    %jmp T_47.5;
T_47.4 ;
    %load/vec4 v00000143743850a0_0;
    %pad/u 32;
    %cmpi/e 63, 0, 32;
    %jmp/0xz  T_47.6, 4;
    %load/vec4 v00000143743864e0_0;
    %load/vec4 v0000014374384240_0;
    %pad/s 32;
    %add;
    %store/vec4 v0000014374388740_0, 0, 32;
    %load/vec4 v0000014374388740_0;
    %assign/vec4 v00000143743864e0_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v00000143743850a0_0, 0;
    %load/vec4 v00000143743841a0_0;
    %assign/vec4 v0000014374386a80_0, 0;
    %load/vec4 v00000143743841a0_0;
    %inv;
    %assign/vec4 v00000143743841a0_0, 0;
    %load/vec4 v0000014374388740_0;
    %ix/load 4, 6, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %assign/vec4 v0000014374385000_0, 0;
    %load/vec4 v0000014374388740_0;
    %ix/load 4, 6, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %pad/s 16;
    %assign/vec4 v00000143743856e0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374384740_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374384420_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v00000143743869e0_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v0000014374387020_0, 0;
    %jmp T_47.7;
T_47.6 ;
    %load/vec4 v00000143743864e0_0;
    %load/vec4 v0000014374384240_0;
    %pad/s 32;
    %add;
    %assign/vec4 v00000143743864e0_0, 0;
    %load/vec4 v00000143743850a0_0;
    %addi 1, 0, 6;
    %assign/vec4 v00000143743850a0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374384740_0, 0;
T_47.7 ;
T_47.5 ;
    %jmp T_47.3;
T_47.2 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374384740_0, 0;
T_47.3 ;
T_47.1 ;
    %jmp T_47;
    .thread T_47;
    .scope S_0000014374322c80;
T_48 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v00000143743881a0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_48.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743869e0_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v0000014374387020_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374386a80_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374384880_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743847e0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374387520_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743849c0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743875c0_0, 0;
    %jmp T_48.1;
T_48.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743875c0_0, 0;
    %load/vec4 v00000143743869e0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_48.2, 8;
    %load/vec4 v0000014374386a80_0;
    %load/vec4 v0000014374387020_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v0000014374386f80, 4;
    %assign/vec4 v0000014374384880_0, 0;
    %load/vec4 v0000014374386a80_0;
    %load/vec4 v0000014374387020_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v0000014374387840, 4;
    %assign/vec4 v00000143743847e0_0, 0;
    %load/vec4 v0000014374386a80_0;
    %load/vec4 v0000014374387020_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v00000143743884c0, 4;
    %assign/vec4 v0000014374387520_0, 0;
    %load/vec4 v0000014374386a80_0;
    %load/vec4 v0000014374387020_0;
    %concat/vec4; draw_concat_vec4
    %pad/u 9;
    %ix/vec4 4;
    %load/vec4a v0000014374386760, 4;
    %assign/vec4 v00000143743849c0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v00000143743875c0_0, 0;
    %load/vec4 v0000014374387020_0;
    %pad/u 32;
    %cmpi/e 63, 0, 32;
    %jmp/0xz  T_48.4, 4;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v0000014374387020_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743869e0_0, 0;
    %jmp T_48.5;
T_48.4 ;
    %load/vec4 v0000014374387020_0;
    %addi 1, 0, 6;
    %assign/vec4 v0000014374387020_0, 0;
T_48.5 ;
T_48.2 ;
T_48.1 ;
    %jmp T_48;
    .thread T_48;
    .scope S_0000014374322c80;
T_49 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v00000143743881a0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_49.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743851e0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374385b40_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374385aa0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374385fa0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374385c80_0, 0;
    %jmp T_49.1;
T_49.0 ;
    %load/vec4 v00000143743875c0_0;
    %assign/vec4 v00000143743851e0_0, 0;
    %load/vec4 v0000014374386b20_0;
    %assign/vec4 v0000014374385b40_0, 0;
    %load/vec4 v0000014374386260_0;
    %assign/vec4 v0000014374385aa0_0, 0;
    %load/vec4 v0000014374386580_0;
    %assign/vec4 v0000014374385fa0_0, 0;
    %load/vec4 v0000014374386120_0;
    %assign/vec4 v0000014374385c80_0, 0;
T_49.1 ;
    %jmp T_49;
    .thread T_49;
    .scope S_0000014374322c80;
T_50 ;
    %wait E_00000143742d1690;
    %load/vec4 v00000143743850a0_0;
    %pad/u 32;
    %cmpi/e 63, 0, 32;
    %flag_get/vec4 4;
    %jmp/0 T_50.2, 4;
    %load/vec4 v00000143743846a0_0;
    %and;
T_50.2;
    %flag_set/vec4 8;
    %jmp/0xz  T_50.0, 8;
    %load/vec4 v00000143743864e0_0;
    %ix/load 4, 6, 0;
    %flag_set/imm 4, 0;
    %shiftr/s 4;
    %vpi_call/w 8 227 "$display", "[DEBUG] Symbol Done. Sum_Err = %d, Avg_Err (Shift 6) = %d", v00000143743864e0_0, S<0,vec4,s32> {1 0 0};
T_50.0 ;
    %jmp T_50;
    .thread T_50;
    .scope S_0000014374322c80;
T_51 ;
    %wait E_00000143742d1690;
    %load/vec4 v00000143743850a0_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %flag_get/vec4 4;
    %jmp/0 T_51.2, 4;
    %load/vec4 v00000143743846a0_0;
    %and;
T_51.2;
    %flag_set/vec4 8;
    %jmp/0xz  T_51.0, 8;
    %vpi_call/w 8 233 "$display", "[DEBUG] ang1 = %d, diff1 = %d", v0000014374385d20_0, v0000014374384920_0 {0 0 0};
T_51.0 ;
    %jmp T_51;
    .thread T_51;
    .scope S_00000143743828c0;
T_52 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v0000014374388100_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_52.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374388060_0, 0;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v00000143743878e0_0, 0;
    %jmp T_52.1;
T_52.0 ;
    %load/vec4 v0000014374387ca0_0;
    %assign/vec4 v0000014374388060_0, 0;
    %load/vec4 v0000014374387ca0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_52.2, 8;
    %load/vec4 v00000143743877a0_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 3, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v00000143743878e0_0, 4, 5;
    %load/vec4 v0000014374386ee0_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 2, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v00000143743878e0_0, 4, 5;
    %load/vec4 v00000143743887e0_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 1, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v00000143743878e0_0, 4, 5;
    %load/vec4 v0000014374387fc0_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v00000143743878e0_0, 4, 5;
T_52.2 ;
T_52.1 ;
    %jmp T_52;
    .thread T_52;
    .scope S_0000014374323130;
T_53 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437439a790_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_53.0, 8;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437439fd30_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437439ff10_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437439a0b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437439fa10_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437439f970_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437439fdd0_0, 0;
    %jmp T_53.1;
T_53.0 ;
    %load/vec4 v00000143743997f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_53.2, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001437439fa10_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437439fd30_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437439ff10_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v000001437439a0b0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437439f970_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437439fdd0_0, 0;
T_53.2 ;
    %load/vec4 v000001437439fa10_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_53.6, 9;
    %load/vec4 v00000143743999d0_0;
    %and;
T_53.6;
    %flag_set/vec4 8;
    %jmp/0xz  T_53.4, 8;
    %load/vec4 v00000143743996b0_0;
    %load/vec4 v000001437439fd30_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437439e9d0, 0, 4;
    %load/vec4 v0000014374399570_0;
    %load/vec4 v000001437439fd30_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437439e930, 0, 4;
    %load/vec4 v0000014374399750_0;
    %load/vec4 v000001437439fd30_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437439ec50, 0, 4;
    %load/vec4 v0000014374399c50_0;
    %load/vec4 v000001437439fd30_0;
    %pad/u 8;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000001437439ea70, 0, 4;
    %load/vec4 v000001437439fd30_0;
    %addi 1, 0, 7;
    %assign/vec4 v000001437439ff10_0, 0;
    %load/vec4 v000001437439fd30_0;
    %cmpi/e 79, 0, 7;
    %jmp/0xz  T_53.7, 4;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v000001437439fa10_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001437439f970_0, 0;
    %pushi/vec4 80, 0, 7;
    %assign/vec4 v000001437439a0b0_0, 0;
T_53.7 ;
    %load/vec4 v000001437439fd30_0;
    %addi 1, 0, 7;
    %assign/vec4 v000001437439fd30_0, 0;
T_53.4 ;
    %load/vec4 v000001437439fc90_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_53.9, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v000001437439fdd0_0, 0;
    %load/vec4 v000001437439f970_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_53.11, 8;
    %pushi/vec4 80, 0, 7;
    %assign/vec4 v000001437439a0b0_0, 0;
T_53.11 ;
T_53.9 ;
T_53.1 ;
    %jmp T_53;
    .thread T_53;
    .scope S_0000014374323130;
T_54 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437439a790_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_54.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374398670_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v00000143743a0050_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743991b0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374399d90_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374398d50_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439a1f0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743992f0_0, 0;
    %jmp T_54.1;
T_54.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743991b0_0, 0;
    %load/vec4 v0000014374398670_0;
    %assign/vec4 v000001437439a470_0, 0;
    %load/vec4 v0000014374398670_0;
    %nor/r;
    %flag_set/vec4 10;
    %flag_get/vec4 10;
    %jmp/0 T_54.5, 10;
    %load/vec4 v000001437439fdd0_0;
    %and;
T_54.5;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_54.4, 9;
    %load/vec4 v000001437439f970_0;
    %and;
T_54.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_54.2, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374398670_0, 0;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v00000143743a0050_0, 0;
T_54.2 ;
    %load/vec4 v000001437439a470_0;
    %nor/r;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_54.8, 9;
    %load/vec4 v0000014374398670_0;
    %and;
T_54.8;
    %flag_set/vec4 8;
    %jmp/0xz  T_54.6, 8;
    %vpi_call/w 4 157 "$display", "[DBG][PLAY] T=%t start play_len=%0d captured_count=%0d wr=%0d rd=%0d", $time, v000001437439a0b0_0, v000001437439ff10_0, v000001437439fd30_0, v00000143743a0050_0 {0 0 0};
T_54.6 ;
    %load/vec4 v0000014374398670_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_54.9, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v00000143743991b0_0, 0;
    %load/vec4 v00000143743a0050_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v000001437439e9d0, 4;
    %assign/vec4 v0000014374399d90_0, 0;
    %load/vec4 v00000143743a0050_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v000001437439e930, 4;
    %assign/vec4 v0000014374398d50_0, 0;
    %load/vec4 v00000143743a0050_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v000001437439ec50, 4;
    %assign/vec4 v000001437439a1f0_0, 0;
    %load/vec4 v00000143743a0050_0;
    %pad/u 8;
    %ix/vec4 4;
    %load/vec4a v000001437439ea70, 4;
    %assign/vec4 v00000143743992f0_0, 0;
    %load/vec4 v00000143743a0050_0;
    %load/vec4 v000001437439a0b0_0;
    %subi 1, 0, 7;
    %cmp/e;
    %jmp/0xz  T_54.11, 4;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374398670_0, 0;
    %jmp T_54.12;
T_54.11 ;
    %load/vec4 v00000143743a0050_0;
    %addi 1, 0, 7;
    %assign/vec4 v00000143743a0050_0, 0;
T_54.12 ;
T_54.9 ;
T_54.1 ;
    %jmp T_54;
    .thread T_54;
    .scope S_0000014374323130;
T_55 ;
    %vpi_func 4 217 "$fopen" 32, "rtl_fft_in_dump.hex", "w" {0 0 0};
    %store/vec4 v0000014374399bb0_0, 0, 32;
    %pushi/vec4 0, 0, 7;
    %store/vec4 v0000014374398990_0, 0, 7;
    %end;
    .thread T_55;
    .scope S_0000014374323130;
T_56 ;
    %wait E_00000143742d1690;
    %load/vec4 v000001437439a790_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_56.0, 8;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374398990_0, 0;
    %jmp T_56.1;
T_56.0 ;
    %load/vec4 v00000143743997f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_56.2, 8;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374398990_0, 0;
    %jmp T_56.3;
T_56.2 ;
    %load/vec4 v000001437439a830_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_56.6, 9;
    %load/vec4 v0000014374398990_0;
    %pad/u 32;
    %cmpi/u 64, 0, 32;
    %flag_get/vec4 5;
    %and;
T_56.6;
    %flag_set/vec4 8;
    %jmp/0xz  T_56.4, 8;
    %load/vec4 v0000014374398850_0;
    %load/vec4 v000001437439a510_0;
    %load/vec4 v0000014374398cb0_0;
    %load/vec4 v0000014374398c10_0;
    %vpi_call/w 4 227 "$fdisplay", v0000014374399bb0_0, "%04h%04h%04h%04h", S<3,vec4,u16>, S<2,vec4,u16>, S<1,vec4,u16>, S<0,vec4,u16> {4 0 0};
    %load/vec4 v0000014374398990_0;
    %addi 1, 0, 7;
    %assign/vec4 v0000014374398990_0, 0;
T_56.4 ;
T_56.3 ;
T_56.1 ;
    %jmp T_56;
    .thread T_56;
    .scope S_0000014374323130;
T_57 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437439a790_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_57.0, 8;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374399930_0, 0;
    %jmp T_57.1;
T_57.0 ;
    %load/vec4 v00000143743997f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_57.2, 8;
    %pushi/vec4 0, 0, 7;
    %assign/vec4 v0000014374399930_0, 0;
    %jmp T_57.3;
T_57.2 ;
    %load/vec4 v000001437439a6f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_57.4, 8;
    %load/vec4 v0000014374399930_0;
    %addi 1, 0, 7;
    %assign/vec4 v0000014374399930_0, 0;
T_57.4 ;
T_57.3 ;
T_57.1 ;
    %jmp T_57;
    .thread T_57;
    .scope S_0000014374323130;
T_58 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437439a790_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_58.0, 8;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0000014374399250_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001437439a010_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374398a30_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374399ed0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743985d0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374398490_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v000001437439a3d0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374399390_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v00000143743983f0_0, 0;
    %jmp T_58.1;
T_58.0 ;
    %load/vec4 v0000014374399250_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 3;
    %cmp/u;
    %jmp/1 T_58.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 3;
    %cmp/u;
    %jmp/1 T_58.3, 6;
    %jmp T_58.4;
T_58.2 ;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001437439a010_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374398a30_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374399ed0_0, 0;
    %load/vec4 v00000143743985d0_0;
    %flag_set/vec4 8;
    %jmp/1 T_58.7, 8;
    %load/vec4 v0000014374399890_0;
    %flag_set/vec4 10;
    %flag_get/vec4 10;
    %jmp/0 T_58.8, 10;
    %load/vec4 v0000014374398530_0;
    %and;
T_58.8;
    %flag_set/vec4 9;
    %flag_or 8, 9;
T_58.7;
    %jmp/0xz  T_58.5, 8;
    %pushi/vec4 1, 0, 3;
    %assign/vec4 v0000014374399250_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374398a30_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v00000143743985d0_0, 0;
T_58.5 ;
    %jmp T_58.4;
T_58.3 ;
    %load/vec4 v0000014374399070_0;
    %assign/vec4 v0000014374398490_0, 0;
    %load/vec4 v0000014374398350_0;
    %assign/vec4 v000001437439a3d0_0, 0;
    %load/vec4 v0000014374398df0_0;
    %assign/vec4 v0000014374399390_0, 0;
    %load/vec4 v0000014374399f70_0;
    %assign/vec4 v00000143743983f0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374399ed0_0, 0;
    %load/vec4 v000001437439a010_0;
    %pad/u 32;
    %cmpi/e 63, 0, 32;
    %jmp/0xz  T_58.9, 4;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0000014374399250_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374398a30_0, 0;
    %pushi/vec4 0, 0, 6;
    %assign/vec4 v000001437439a010_0, 0;
    %jmp T_58.10;
T_58.9 ;
    %load/vec4 v000001437439a010_0;
    %addi 1, 0, 6;
    %assign/vec4 v000001437439a010_0, 0;
T_58.10 ;
    %load/vec4 v0000014374399890_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_58.13, 9;
    %load/vec4 v0000014374398530_0;
    %and;
T_58.13;
    %flag_set/vec4 8;
    %jmp/0xz  T_58.11, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v00000143743985d0_0, 0;
T_58.11 ;
    %jmp T_58.4;
T_58.4 ;
    %pop/vec4 1;
T_58.1 ;
    %jmp T_58;
    .thread T_58;
    .scope S_0000014374323130;
T_59 ;
    %wait E_00000143742d2ad0;
    %load/vec4 v000001437439a790_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0000014374398b70_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374399430_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374399e30_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374399cf0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374398fd0_0, 0;
    %pushi/vec4 0, 0, 16;
    %assign/vec4 v0000014374399a70_0, 0;
    %jmp T_59.1;
T_59.0 ;
    %load/vec4 v000001437439a650_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.2, 8;
    %vpi_call/w 4 419 "$display", "[DBG][ADC ] T=%t idx=%0d in1=(%0d,%0d) in2=(%0d,%0d)", $time, v0000014374399430_0, v000001437439e6b0_0, v000001437439e610_0, v000001437439e7f0_0, v000001437439e750_0 {0 0 0};
T_59.2 ;
    %load/vec4 v000001437439a650_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.4, 8;
    %load/vec4 v0000014374399430_0;
    %addi 1, 0, 16;
    %assign/vec4 v0000014374399430_0, 0;
T_59.4 ;
    %load/vec4 v00000143743997f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.6, 8;
    %vpi_call/w 4 424 "$display", "[DBG][SYNC] T=%t best_symbol_start asserted (sym_sample_idx=%0d)", $time, v0000014374399930_0 {0 0 0};
T_59.6 ;
    %load/vec4 v000001437439fc90_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.8, 8;
    %vpi_call/w 4 427 "$display", "[DBG][CFO ] T=%t eps_hat=%0d", $time, v000001437439fe70_0 {0 0 0};
T_59.8 ;
    %load/vec4 v000001437439a6f0_0;
    %flag_set/vec4 10;
    %flag_get/vec4 10;
    %jmp/0 T_59.13, 10;
    %load/vec4 v000001437439a830_0;
    %and;
T_59.13;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_59.12, 9;
    %load/vec4 v0000014374399e30_0;
    %pad/u 32;
    %cmpi/u 80, 0, 32;
    %flag_get/vec4 5;
    %and;
T_59.12;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.10, 8;
    %vpi_call/w 4 430 "$display", "[DBG][FFT_IN] T=%t idx=%0d load_re1=%0d load_im1=%0d load_re2=%0d load_im2=%0d", $time, v0000014374399930_0, v0000014374398850_0, v000001437439a510_0, v0000014374398cb0_0, v0000014374398c10_0 {0 0 0};
    %load/vec4 v0000014374399e30_0;
    %addi 1, 0, 16;
    %assign/vec4 v0000014374399e30_0, 0;
T_59.10 ;
    %load/vec4 v0000014374399890_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.14, 8;
    %vpi_call/w 4 436 "$display", "[DBG][FFT ] T=%t: FFT1 Done Pulse!", $time {0 0 0};
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0000014374398b70_0, 0;
T_59.14 ;
    %load/vec4 v0000014374399250_0;
    %pad/u 32;
    %cmpi/e 1, 0, 32;
    %flag_get/vec4 4;
    %jmp/0 T_59.19, 4;
    %load/vec4 v0000014374399ed0_0;
    %and;
T_59.19;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_59.18, 9;
    %load/vec4 v0000014374399cf0_0;
    %pad/u 32;
    %cmpi/u 64, 0, 32;
    %flag_get/vec4 5;
    %and;
T_59.18;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.16, 8;
    %vpi_call/w 4 440 "$display", "[DBG][FFT_OUT] T=%t addr=%0d y1=(%0d,%0d) y2=(%0d,%0d)", $time, v000001437439a010_0, v0000014374398490_0, v000001437439a3d0_0, v0000014374399390_0, v00000143743983f0_0 {0 0 0};
    %load/vec4 v0000014374399cf0_0;
    %addi 1, 0, 16;
    %assign/vec4 v0000014374399cf0_0, 0;
T_59.16 ;
    %load/vec4 v000001437439a8d0_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_59.22, 9;
    %load/vec4 v0000014374398fd0_0;
    %pad/u 32;
    %cmpi/u 64, 0, 32;
    %flag_get/vec4 5;
    %and;
T_59.22;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.20, 8;
    %vpi_call/w 4 446 "$display", "[DBG][ZF  ] T=%t k=%0d X1=(%0d,%0d) X2=(%0d,%0d)", $time, v0000014374398fd0_0, v000001437439d490_0, v000001437439d7b0_0, v000001437439d850_0, v000001437439d5d0_0 {0 0 0};
    %load/vec4 v0000014374398fd0_0;
    %addi 1, 0, 16;
    %assign/vec4 v0000014374398fd0_0, 0;
T_59.20 ;
    %load/vec4 v000001437439fab0_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_59.25, 9;
    %load/vec4 v0000014374399a70_0;
    %pad/u 32;
    %cmpi/u 64, 0, 32;
    %flag_get/vec4 5;
    %and;
T_59.25;
    %flag_set/vec4 8;
    %jmp/0xz  T_59.23, 8;
    %vpi_call/w 4 452 "$display", "[DBG][CPE ] T=%t k=%0d X1c=(%0d,%0d) X2c=(%0d,%0d) phase_err_valid=%b phase_err=%0d", $time, v0000014374399a70_0, v000001437439d670_0, v000001437439d530_0, v000001437439e890_0, v000001437439d990_0, v0000014374398710_0, v000001437439fb50_0 {0 0 0};
    %load/vec4 v0000014374399a70_0;
    %addi 1, 0, 16;
    %assign/vec4 v0000014374399a70_0, 0;
T_59.23 ;
T_59.1 ;
    %jmp T_59;
    .thread T_59;
    .scope S_00000143743227d0;
T_60 ;
    %delay 5000, 0;
    %load/vec4 v00000143743a3ba0_0;
    %inv;
    %store/vec4 v00000143743a3ba0_0, 0, 1;
    %jmp T_60;
    .thread T_60;
    .scope S_00000143743227d0;
T_61 ;
    %vpi_call/w 3 83 "$readmemh", "golden_adc_time.hex", v00000143743a3a60 {0 0 0};
    %vpi_call/w 3 84 "$readmemh", "golden_h_inv.hex", v00000143743a3e20 {0 0 0};
    %vpi_call/w 3 85 "$readmemh", "golden_final_out.hex", v00000143743a3d80 {0 0 0};
    %vpi_call/w 3 86 "$readmemh", "golden_zf_out.hex", v00000143743a4e60 {0 0 0};
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000143743a3ba0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000143743a4820_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000143743a4780_0, 0, 1;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a4500_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a4dc0_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a3600_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a3380_0, 0, 16;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %load/vec4a v00000143743a3e20, 4;
    %split/vec4 16;
    %store/vec4 v00000143743a37e0_0, 0, 16;
    %store/vec4 v00000143743a46e0_0, 0, 16;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %load/vec4a v00000143743a3e20, 4;
    %split/vec4 16;
    %store/vec4 v00000143743a4960_0, 0, 16;
    %store/vec4 v00000143743a2980_0, 0, 16;
    %ix/load 4, 2, 0;
    %flag_set/imm 4, 0;
    %load/vec4a v00000143743a3e20, 4;
    %split/vec4 16;
    %store/vec4 v00000143743a4fa0_0, 0, 16;
    %store/vec4 v00000143743a3100_0, 0, 16;
    %ix/load 4, 3, 0;
    %flag_set/imm 4, 0;
    %load/vec4a v00000143743a3e20, 4;
    %split/vec4 16;
    %store/vec4 v00000143743a3c40_0, 0, 16;
    %store/vec4 v00000143743a3880_0, 0, 16;
    %vpi_call/w 3 100 "$display", "-------------------------------------------" {0 0 0};
    %vpi_call/w 3 101 "$display", "   TOP LEVEL VERIFICATION START            " {0 0 0};
    %vpi_call/w 3 102 "$display", "-------------------------------------------" {0 0 0};
    %vpi_call/w 3 103 "$display", "Loading H Matrix:" {0 0 0};
    %vpi_call/w 3 104 "$display", "H00 = %d + j%d", v00000143743a46e0_0, v00000143743a37e0_0 {0 0 0};
    %delay 100000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000143743a4820_0, 0, 1;
    %delay 50000, 0;
    %vpi_call/w 3 112 "$display", "Feeding ADC Data..." {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a2e80_0, 0, 32;
T_61.0 ;
    %load/vec4 v00000143743a2e80_0;
    %cmpi/s 80, 0, 32;
    %jmp/0xz T_61.1, 5;
    %wait E_00000143742d1690;
    %delay 1000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000143743a4780_0, 0, 1;
    %ix/getv/s 4, v00000143743a2e80_0;
    %load/vec4a v00000143743a3a60, 4;
    %split/vec4 16;
    %store/vec4 v00000143743a3380_0, 0, 16;
    %split/vec4 16;
    %store/vec4 v00000143743a3600_0, 0, 16;
    %split/vec4 16;
    %store/vec4 v00000143743a4dc0_0, 0, 16;
    %store/vec4 v00000143743a4500_0, 0, 16;
    %load/vec4 v00000143743a2e80_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a2e80_0, 0, 32;
    %jmp T_61.0;
T_61.1 ;
    %vpi_call/w 3 126 "$display", "Feeding Dummy Data to flush pipeline..." {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a2e80_0, 0, 32;
T_61.2 ;
    %load/vec4 v00000143743a2e80_0;
    %cmpi/s 84, 0, 32;
    %jmp/0xz T_61.3, 5;
    %wait E_00000143742d1690;
    %delay 1000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v00000143743a4780_0, 0, 1;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a4500_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a4dc0_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a3600_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a3380_0, 0, 16;
    %load/vec4 v00000143743a2e80_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a2e80_0, 0, 32;
    %jmp T_61.2;
T_61.3 ;
    %wait E_00000143742d1690;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v00000143743a4780_0, 0, 1;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a4500_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a4dc0_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a3600_0, 0, 16;
    %pushi/vec4 0, 0, 16;
    %store/vec4 v00000143743a3380_0, 0, 16;
    %vpi_call/w 3 140 "$display", "Data Feed Done. Waiting for Output..." {0 0 0};
    %delay 5000000, 0;
    %vpi_call/w 3 146 "$display", "-------------------------------------------" {0 0 0};
    %vpi_call/w 3 147 "$display", "   SIMULATION FINISHED                     " {0 0 0};
    %vpi_call/w 3 148 "$display", "-------------------------------------------" {0 0 0};
    %vpi_call/w 3 149 "$finish" {0 0 0};
    %end;
    .thread T_61;
    .scope S_00000143743227d0;
T_62 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a2b60_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a4f00_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a4aa0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a4a00_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a5040_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a48c0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a36a0_0, 0, 32;
    %end;
    .thread T_62;
    .scope S_00000143743227d0;
T_63 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a45a0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a3060_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a3b00_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a39c0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a4be0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a3420_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a3920_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v00000143743a2de0_0, 0, 32;
    %end;
    .thread T_63;
    .scope S_00000143743227d0;
T_64 ;
    %wait E_00000143742d1690;
    %load/vec4 v00000143743a40a0_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_64.2, 9;
    %load/vec4 v00000143743a4a00_0;
    %cmpi/s 64, 0, 32;
    %flag_get/vec4 5;
    %and;
T_64.2;
    %flag_set/vec4 8;
    %jmp/0xz  T_64.0, 8;
    %ix/getv/s 4, v00000143743a4a00_0;
    %load/vec4a v00000143743a4e60, 4;
    %split/vec4 16;
    %store/vec4 v00000143743a4280_0, 0, 16;
    %split/vec4 16;
    %store/vec4 v00000143743a4460_0, 0, 16;
    %split/vec4 16;
    %store/vec4 v00000143743a4640_0, 0, 16;
    %store/vec4 v00000143743a3740_0, 0, 16;
    %vpi_call/w 3 193 "$display", "[TB][ZF ] t=%t k=%0d DUT=(%0d,%0d)(%0d,%0d) GOLD=(%0d,%0d)(%0d,%0d)", $time, v00000143743a4a00_0, v00000143743a4140_0, v00000143743a4320_0, v00000143743a2c00_0, v00000143743a41e0_0, v00000143743a3740_0, v00000143743a4640_0, v00000143743a4460_0, v00000143743a4280_0 {0 0 0};
    %load/vec4 v00000143743a45a0_0;
    %load/vec4 v00000143743a3740_0;
    %load/vec4 v00000143743a4140_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %add;
    %store/vec4 v00000143743a45a0_0, 0, 32;
    %load/vec4 v00000143743a3060_0;
    %load/vec4 v00000143743a4640_0;
    %load/vec4 v00000143743a4320_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %add;
    %store/vec4 v00000143743a3060_0, 0, 32;
    %load/vec4 v00000143743a3b00_0;
    %load/vec4 v00000143743a4460_0;
    %load/vec4 v00000143743a2c00_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %add;
    %store/vec4 v00000143743a3b00_0, 0, 32;
    %load/vec4 v00000143743a39c0_0;
    %load/vec4 v00000143743a4280_0;
    %load/vec4 v00000143743a41e0_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %add;
    %store/vec4 v00000143743a39c0_0, 0, 32;
    %load/vec4 v00000143743a4be0_0;
    %load/vec4 v00000143743a3740_0;
    %load/vec4 v00000143743a4140_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %cmp/s;
    %jmp/0xz  T_64.3, 5;
    %load/vec4 v00000143743a3740_0;
    %load/vec4 v00000143743a4140_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %store/vec4 v00000143743a4be0_0, 0, 32;
T_64.3 ;
    %load/vec4 v00000143743a3420_0;
    %load/vec4 v00000143743a4640_0;
    %load/vec4 v00000143743a4320_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %cmp/s;
    %jmp/0xz  T_64.5, 5;
    %load/vec4 v00000143743a4640_0;
    %load/vec4 v00000143743a4320_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %store/vec4 v00000143743a3420_0, 0, 32;
T_64.5 ;
    %load/vec4 v00000143743a3920_0;
    %load/vec4 v00000143743a4460_0;
    %load/vec4 v00000143743a2c00_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %cmp/s;
    %jmp/0xz  T_64.7, 5;
    %load/vec4 v00000143743a4460_0;
    %load/vec4 v00000143743a2c00_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %store/vec4 v00000143743a3920_0, 0, 32;
T_64.7 ;
    %load/vec4 v00000143743a2de0_0;
    %load/vec4 v00000143743a4280_0;
    %load/vec4 v00000143743a41e0_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %cmp/s;
    %jmp/0xz  T_64.9, 5;
    %load/vec4 v00000143743a4280_0;
    %load/vec4 v00000143743a41e0_0;
    %sub;
    %store/vec4 v00000143742e4d70_0, 0, 16;
    %callf/vec4 TD_tb_top_receiver.abs16, S_0000014374323450;
    %store/vec4 v00000143743a2de0_0, 0, 32;
T_64.9 ;
    %load/vec4 v00000143743a3740_0;
    %load/vec4 v00000143743a4140_0;
    %cmp/ne;
    %jmp/1 T_64.15, 6;
    %flag_mov 8, 6;
    %load/vec4 v00000143743a4640_0;
    %load/vec4 v00000143743a4320_0;
    %cmp/ne;
    %flag_or 6, 8;
T_64.15;
    %jmp/1 T_64.14, 6;
    %flag_mov 8, 6;
    %load/vec4 v00000143743a4460_0;
    %load/vec4 v00000143743a2c00_0;
    %cmp/ne;
    %flag_or 6, 8;
T_64.14;
    %jmp/1 T_64.13, 6;
    %flag_mov 8, 6;
    %load/vec4 v00000143743a4280_0;
    %load/vec4 v00000143743a41e0_0;
    %cmp/ne;
    %flag_or 6, 8;
T_64.13;
    %jmp/0xz  T_64.11, 6;
    %load/vec4 v00000143743a5040_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a5040_0, 0, 32;
    %vpi_call/w 3 209 "$display", "[ZFCHK][%0d] T=%t DUT=(%d,%d)(%d,%d) GOLD=(%d,%d)(%d,%d)", v00000143743a4a00_0, $time, v00000143743a4140_0, v00000143743a4320_0, v00000143743a2c00_0, v00000143743a41e0_0, v00000143743a3740_0, v00000143743a4640_0, v00000143743a4460_0, v00000143743a4280_0 {0 0 0};
    %jmp T_64.12;
T_64.11 ;
    %load/vec4 v00000143743a48c0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a48c0_0, 0, 32;
T_64.12 ;
    %load/vec4 v00000143743a4a00_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a4a00_0, 0, 32;
T_64.0 ;
    %jmp T_64;
    .thread T_64;
    .scope S_00000143743227d0;
T_65 ;
    %wait E_00000143742d1690;
    %load/vec4 v00000143743a4780_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_65.0, 8;
    %vpi_call/w 3 222 "$display", "[TB][ADC] t=%t idx=%0d adc1=(%0d,%0d) adc2=(%0d,%0d)", $time, v00000143743a36a0_0, v00000143743a4500_0, v00000143743a4dc0_0, v00000143743a3600_0, v00000143743a3380_0 {0 0 0};
    %load/vec4 v00000143743a36a0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a36a0_0, 0, 32;
T_65.0 ;
    %load/vec4 v00000143743a3f60_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_65.4, 9;
    %load/vec4 v00000143743a2b60_0;
    %cmpi/s 64, 0, 32;
    %flag_get/vec4 5;
    %and;
T_65.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_65.2, 8;
    %ix/getv/s 4, v00000143743a2b60_0;
    %load/vec4a v00000143743a3d80, 4;
    %split/vec4 16;
    %store/vec4 v00000143743a50e0_0, 0, 16;
    %split/vec4 16;
    %store/vec4 v00000143743a32e0_0, 0, 16;
    %split/vec4 16;
    %store/vec4 v00000143743a4d20_0, 0, 16;
    %store/vec4 v00000143743a4c80_0, 0, 16;
    %load/vec4 v00000143743a4c80_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 3, 0;
    %flag_set/imm 4, 0;
    %store/vec4 v00000143743a3240_0, 4, 1;
    %load/vec4 v00000143743a4d20_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 2, 0;
    %flag_set/imm 4, 0;
    %store/vec4 v00000143743a3240_0, 4, 1;
    %load/vec4 v00000143743a32e0_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %store/vec4 v00000143743a3240_0, 4, 1;
    %load/vec4 v00000143743a50e0_0;
    %pad/s 32;
    %cmpi/s 0, 0, 32;
    %flag_get/vec4 5;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4 v00000143743a3240_0, 4, 1;
    %load/vec4 v00000143743a3240_0;
    %load/vec4 v00000143743a2ca0_0;
    %cmp/ne;
    %jmp/0xz  T_65.5, 6;
    %load/vec4 v00000143743a4f00_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a4f00_0, 0, 32;
    %vpi_call/w 3 234 "$display", "[CHECK][%0d] Time %t: DUT=%b GOLD=%b", v00000143743a2b60_0, $time, v00000143743a2ca0_0, v00000143743a3240_0 {0 0 0};
    %jmp T_65.6;
T_65.5 ;
    %vpi_call/w 3 236 "$display", "[CHECK][%0d] Time %t: Match %b", v00000143743a2b60_0, $time, v00000143743a2ca0_0 {0 0 0};
    %load/vec4 v00000143743a4aa0_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a4aa0_0, 0, 32;
T_65.6 ;
    %load/vec4 v00000143743a2b60_0;
    %addi 1, 0, 32;
    %store/vec4 v00000143743a2b60_0, 0, 32;
T_65.2 ;
    %jmp T_65;
    .thread T_65;
    .scope S_00000143743227d0;
T_66 ;
T_66.0 ;
    %load/vec4 v00000143743a4820_0;
    %pushi/vec4 1, 0, 1;
    %cmp/e;
    %flag_get/vec4 6;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_66.1, 6;
    %wait E_00000143742d1b10;
    %jmp T_66.0;
T_66.1 ;
T_66.2 ;
    %load/vec4 v00000143743a2b60_0;
    %pushi/vec4 64, 0, 32;
    %cmp/e;
    %flag_get/vec4 4;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_66.3, 6;
    %wait E_00000143742d2010;
    %jmp T_66.2;
T_66.3 ;
    %vpi_call/w 3 247 "$display", "================================================" {0 0 0};
    %vpi_call/w 3 248 "$display", "Golden compare done: %0d mismatches / %0d matches over %0d outputs", v00000143743a4f00_0, v00000143743a4aa0_0, P_00000143742ade10 {0 0 0};
    %load/vec4 v00000143743a4f00_0;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_66.4, 4;
    %vpi_call/w 3 250 "$display", "STATUS: PASS" {0 0 0};
    %jmp T_66.5;
T_66.4 ;
    %vpi_call/w 3 252 "$display", "STATUS: FAIL" {0 0 0};
T_66.5 ;
    %vpi_call/w 3 253 "$display", "ZF compare: %0d mismatches / %0d matches over %0d outputs", v00000143743a5040_0, v00000143743a48c0_0, P_00000143742ade10 {0 0 0};
    %load/vec4 v00000143743a45a0_0;
    %cvt/rv/s;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %load/vec4 v00000143743a3060_0;
    %cvt/rv/s;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %load/vec4 v00000143743a3b00_0;
    %cvt/rv/s;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %load/vec4 v00000143743a39c0_0;
    %cvt/rv/s;
    %pushi/real 1073741824, 4072; load=64.0000
    %div/wr;
    %vpi_call/w 3 254 "$display", "ZF avg abs err X1_re=%0f X1_im=%0f X2_re=%0f X2_im=%0f", W<3,r>, W<2,r>, W<1,r>, W<0,r> {0 4 0};
    %vpi_call/w 3 256 "$display", "ZF max abs err X1_re=%0d X1_im=%0d X2_re=%0d X2_im=%0d", v00000143743a4be0_0, v00000143743a3420_0, v00000143743a3920_0, v00000143743a2de0_0 {0 0 0};
    %vpi_call/w 3 258 "$display", "================================================" {0 0 0};
    %end;
    .thread T_66;
    .scope S_00000143743227d0;
T_67 ;
    %wait E_00000143742d1690;
    %load/vec4 v00000143743a3560_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_67.0, 8;
    %vpi_call/w 3 265 "$display", "[DBG][CPE->NCO] T=%t phase_err=%d nco_acc_before=%d", $time, v00000143743a43c0_0, v00000143743a3ec0_0 {0 0 0};
T_67.0 ;
    %jmp T_67;
    .thread T_67;
    .scope S_00000143743227d0;
T_68 ;
    %vpi_call/w 3 272 "$dumpfile", "top_level.vcd" {0 0 0};
    %vpi_call/w 3 273 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000143743227d0 {0 0 0};
    %end;
    .thread T_68;
# The file index is used to find the file name in the following table.
:file_names 16;
    "N/A";
    "<interactive>";
    "-";
    "tb_top_receiver.v";
    "Top_level_receiver.v";
    "CFO_estimator_cp_mrc.v";
    "c_mul_fx.v";
    "cordic_vectoring.v";
    "CPE_tracker.v";
    "cordic_rotator.v";
    "QPSK_demap_mimo.v";
    "fft_64pt.v";
    "nco_phase_ctrl.v";
    "CFO_rotator.v";
    "sync_block.v";
    "mimo_zf_2x2.v";