If Access Memory abstract commands (defined by the debug spec) are supported on a CHERI hart, what should be the effect of the write operation on the capability tag?
Should the semantics of the store instructions from the CHERI spec apply to this case? Quoted below:
All store instructions, except for the RVY SY, always write zero to the capability tag or capability tags associated with the memory locations that are written to. Therefore, misaligned stores may clear up to two associated capability tag bits.
If Access Memory abstract commands (defined by the debug spec) are supported on a CHERI hart, what should be the effect of the write operation on the capability tag?
Should the semantics of the store instructions from the CHERI spec apply to this case? Quoted below: