treewide: Optimizations for faster Verilator simulation (#259) #398
phsauterAnnotations
4 warnings
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[verible-verilog-lint] src/lzc.sv#L61:
src/lzc.sv#L61
All generate block statements must have a label [Style: generate-statements] [generate-label]
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[verible-verilog-lint] src/rr_arb_tree.sv#L125:
src/rr_arb_tree.sv#L125
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
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[verible-verilog-lint] src/rr_arb_tree.sv#L127:
src/rr_arb_tree.sv#L127
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
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[verible-verilog-lint] src/rr_arb_tree.sv#L128:
src/rr_arb_tree.sv#L128
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
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Artifacts
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verible-linter
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338 Bytes |
sha256:200f2466c5ede35ca7a89987bc5eafb5c52f75bf3ccdfe8dc7a287ae4891a4d4
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