Skip to content

Commit 5a15312

Browse files
collucacolluca
committed
Bump mcast modules to common_cells v2
1 parent 19d1845 commit 5a15312

11 files changed

Lines changed: 44 additions & 87 deletions

‎src/axi_demux_simple.sv‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,6 @@ module axi_demux_simple #(
5555
) (
5656
input logic clk_i,
5757
input logic rst_ni,
58-
input logic test_i,
5958
// Slave Port
6059
input axi_req_t slv_req_i,
6160
input select_t slv_aw_select_i,
@@ -84,7 +83,6 @@ module axi_demux_simple #(
8483
) i_axi_mcast_demux_simple (
8584
.clk_i (clk_i),
8685
.rst_ni (rst_ni),
87-
.test_i (test_i),
8886
.slv_req_i (slv_req_i),
8987
.slv_aw_select_i (aw_select_mask),
9088
.slv_aw_addr_i ('0),

‎src/axi_mcast_demux_mapped.sv‎

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,6 @@ module axi_mcast_demux_mapped #(
7070
) (
7171
input logic clk_i,
7272
input logic rst_ni,
73-
input logic test_i,
7473
// Addressing rules
7574
input rule_t [NoAddrRules-1:0] addr_map_i,
7675
input logic en_default_mst_port_i,
@@ -88,8 +87,8 @@ module axi_mcast_demux_mapped #(
8887
// Account for additional error slave
8988
localparam int unsigned NoMstPortsExt = NoMstPorts + 1;
9089

91-
localparam int unsigned IdxSelectWidth = cf_math_pkg::idx_width(NoMstPorts);
92-
localparam int unsigned IdxSelectWidthExt = cf_math_pkg::idx_width(NoMstPortsExt);
90+
localparam int unsigned IdxSelectWidth = cc_pkg::idx_width(NoMstPorts);
91+
localparam int unsigned IdxSelectWidthExt = cc_pkg::idx_width(NoMstPortsExt);
9392
typedef logic [IdxSelectWidth-1:0] idx_select_t;
9493
typedef logic [IdxSelectWidthExt-1:0] idx_select_ext_t;
9594

@@ -110,7 +109,7 @@ module axi_mcast_demux_mapped #(
110109
axi_req_t slv_req_cut;
111110
axi_resp_t slv_resp_cut;
112111

113-
spill_register #(
112+
cc_spill_register #(
114113
.T ( aw_chan_t ),
115114
.Bypass ( ~SpillAw )
116115
) i_aw_spill_reg (
@@ -123,7 +122,7 @@ module axi_mcast_demux_mapped #(
123122
.ready_i ( slv_resp_cut.aw_ready ),
124123
.data_o ( slv_req_cut.aw )
125124
);
126-
spill_register #(
125+
cc_spill_register #(
127126
.T ( w_chan_t ),
128127
.Bypass ( ~SpillW )
129128
) i_w_spill_reg (
@@ -136,7 +135,7 @@ module axi_mcast_demux_mapped #(
136135
.ready_i ( slv_resp_cut.w_ready ),
137136
.data_o ( slv_req_cut.w )
138137
);
139-
spill_register #(
138+
cc_spill_register #(
140139
.T ( ar_chan_t ),
141140
.Bypass ( ~SpillAr )
142141
) i_ar_spill_reg (
@@ -149,7 +148,7 @@ module axi_mcast_demux_mapped #(
149148
.ready_i ( slv_resp_cut.ar_ready ),
150149
.data_o ( slv_req_cut.ar )
151150
);
152-
spill_register #(
151+
cc_spill_register #(
153152
.T ( b_chan_t ),
154153
.Bypass ( ~SpillB )
155154
) i_b_spill_reg (
@@ -162,7 +161,7 @@ module axi_mcast_demux_mapped #(
162161
.ready_i ( slv_req_i.b_ready ),
163162
.data_o ( slv_resp_o.b )
164163
);
165-
spill_register #(
164+
cc_spill_register #(
166165
.T ( r_chan_t ),
167166
.Bypass ( ~SpillR )
168167
) i_r_spill_reg (
@@ -185,7 +184,7 @@ module axi_mcast_demux_mapped #(
185184
idx_select_ext_t ar_select_idx;
186185

187186
// Address decoding for unicast requests
188-
addr_decode #(
187+
cc_addr_decode #(
189188
.NoIndices (NoMstPorts),
190189
.NoRules (NoAddrRules),
191190
.addr_t (addr_t),
@@ -229,7 +228,7 @@ module axi_mcast_demux_mapped #(
229228
addr_t [NoMstPortsExt-1:0] dec_aw_mask;
230229

231230
// Address decoding for unicast requests
232-
addr_decode #(
231+
cc_addr_decode #(
233232
.NoIndices (NoMstPorts),
234233
.NoRules (NoAddrRules),
235234
.addr_t (addr_t),
@@ -348,7 +347,6 @@ module axi_mcast_demux_mapped #(
348347
) i_mcast_demux_simple (
349348
.clk_i,
350349
.rst_ni,
351-
.test_i,
352350
.slv_req_i ( slv_req_cut ),
353351
.slv_aw_select_i ( dec_aw_select_mask ),
354352
.slv_aw_addr_i ( dec_aw_addr ),
@@ -373,7 +371,6 @@ module axi_mcast_demux_mapped #(
373371
) i_axi_err_slv (
374372
.clk_i,
375373
.rst_ni,
376-
.test_i,
377374
.slv_req_i ( errslv_req ),
378375
.slv_resp_o ( errslv_resp )
379376
);
@@ -469,7 +466,6 @@ module axi_mcast_demux_intf #(
469466
) (
470467
input logic clk_i, // Clock
471468
input logic rst_ni, // Asynchronous reset active low
472-
input logic test_i, // Testmode enable
473469
input rule_t [NO_MST_PORTS-2:0] addr_map_i,
474470
input idx_select_t slv_ar_select_i, // has to be stable, when ar_valid
475471
input logic en_default_mst_port_i,
@@ -530,7 +526,6 @@ module axi_mcast_demux_intf #(
530526
) i_axi_demux (
531527
.clk_i, // Clock
532528
.rst_ni, // Asynchronous reset active low
533-
.test_i, // Testmode enable
534529
.addr_map_i ( addr_map_i ),
535530
.en_default_mst_port_i ( en_default_mst_port_i ),
536531
.default_mst_port_i ( default_mst_port_i ),

‎src/axi_mcast_demux_simple.sv‎

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,6 @@ module axi_mcast_demux_simple #(
6060
) (
6161
input logic clk_i,
6262
input logic rst_ni,
63-
input logic test_i,
6463
// Slave Port
6564
input axi_req_t slv_req_i,
6665
input mask_select_t slv_aw_select_i,
@@ -75,7 +74,7 @@ module axi_mcast_demux_simple #(
7574
output logic [NoMstPorts-1:0] mst_aw_commit_o
7675
);
7776

78-
localparam int unsigned IdCounterWidth = cf_math_pkg::idx_width(MaxTrans);
77+
localparam int unsigned IdCounterWidth = cc_pkg::idx_width(MaxTrans);
7978
typedef logic [IdCounterWidth-1:0] id_cnt_t;
8079

8180
localparam int unsigned McastCounterWidth = (MaxMcastTrans > 32'd1) ? $clog2(MaxMcastTrans+1) : 32'd1;
@@ -233,7 +232,7 @@ module axi_mcast_demux_simple #(
233232

234233
// lock the valid signal, as the selection gets pushed into the W FIFO on first assertion,
235234
// prevent further pushing
236-
`FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
235+
`FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni)
237236

238237
//--------------------------------------
239238
// Multicast logic
@@ -244,15 +243,15 @@ module axi_mcast_demux_simple #(
244243
// the ID counters. We anyways don't use the ID counters on
245244
// multicast transactions...
246245

247-
onehot_to_bin #(
246+
cc_onehot_to_bin #(
248247
.ONEHOT_WIDTH(NoMstPorts)
249248
) i_onehot_to_bin (
250249
.onehot(slv_aw_select_i & {NoMstPorts{!aw_is_multicast}}),
251250
.bin (slv_aw_select)
252251
);
253252

254253
// Popcount to identify multicast requests
255-
popcount #(NoMstPorts) i_aw_select_popcount (
254+
cc_popcount #(NoMstPorts) i_aw_select_popcount (
256255
.data_i (slv_aw_select_i),
257256
.popcount_o(aw_select_popcount)
258257
);
@@ -287,8 +286,8 @@ module axi_mcast_demux_simple #(
287286
assign mst_is_mcast_o = {NoMstPorts{aw_is_multicast}};
288287

289288
// Keep track of which B responses need to be returned to complete the multicast
290-
`FFARN(multicast_select_q, multicast_select_d, '0, clk_i, rst_ni)
291-
`FFARN(outstanding_mcast_cnt_q, outstanding_mcast_cnt_d, '0, clk_i, rst_ni)
289+
`FF(multicast_select_q, multicast_select_d, '0, clk_i, rst_ni)
290+
`FF(outstanding_mcast_cnt_q, outstanding_mcast_cnt_d, '0, clk_i, rst_ni)
292291

293292
// Logic to update number of outstanding multicast transactions and current multicast
294293
// transactions' select mask. Counter is incremented upon the AW handshake of a multicast
@@ -332,7 +331,7 @@ module axi_mcast_demux_simple #(
332331

333332
assign mcast_aw_hs_in_progress = mcast_aw_hs_state_q == MCastAwHandshakeInProgress;
334333

335-
`FFARN(mcast_aw_hs_state_q, mcast_aw_hs_state_d, MCastAwHandshakeIdle, clk_i, rst_ni)
334+
`FF(mcast_aw_hs_state_q, mcast_aw_hs_state_d, MCastAwHandshakeIdle, clk_i, rst_ni)
336335

337336
// When a multicast occurs, the upstream valid signals need to
338337
// be forwarded to multiple master ports.
@@ -391,7 +390,7 @@ module axi_mcast_demux_simple #(
391390
// `w_select` determines, which handshaking is connected.
392391
// AWs are only forwarded, if the counter is empty, or `w_select_q` is the same as
393392
// `slv_aw_select_i`.
394-
counter #(
393+
cc_counter #(
395394
.WIDTH ( IdCounterWidth ),
396395
.STICKY_OVERFLOW ( 1'b0 )
397396
) i_counter_open_w (
@@ -406,7 +405,7 @@ module axi_mcast_demux_simple #(
406405
.overflow_o ( /*not used*/ )
407406
);
408407

409-
`FFLARN(w_select_q, slv_aw_select_i, w_cnt_up, mask_select_t'(0), clk_i, rst_ni)
408+
`FFL(w_select_q, slv_aw_select_i, w_cnt_up, mask_select_t'(0), clk_i, rst_ni)
410409
assign w_select = (|w_open) ? w_select_q : slv_aw_select_i;
411410
assign w_select_valid = w_cnt_up | (|w_open);
412411
assign w_cnt_down = slv_req_i.w_valid & slv_resp_o.w_ready & slv_req_i.w.last;
@@ -418,7 +417,7 @@ module axi_mcast_demux_simple #(
418417
// When a multicast occurs, the upstream valid signals need to
419418
// be forwarded to multiple master ports.
420419
// Proper stream forking is necessary to avoid protocol violations
421-
stream_fork_dynamic #(
420+
cc_stream_fork_dynamic #(
422421
.N_OUP(NoMstPorts)
423422
) i_w_stream_fork_dynamic (
424423
.clk_i (clk_i),
@@ -435,10 +434,10 @@ module axi_mcast_demux_simple #(
435434
//--------------------------------------
436435
// B Channel
437436
//--------------------------------------
438-
logic [cf_math_pkg::idx_width(NoMstPorts)-1:0] b_idx;
437+
logic [cc_pkg::idx_width(NoMstPorts)-1:0] b_idx;
439438

440439
// Arbitration of the different B responses
441-
rr_arb_tree #(
440+
cc_rr_arb_tree #(
442441
.NumIn ( NoMstPorts ),
443442
.DataType ( logic ),
444443
.AxiVldRdy( 1'b1 ),
@@ -458,7 +457,7 @@ module axi_mcast_demux_simple #(
458457
);
459458

460459
// Streams must be joined instead of arbitrated when multicast
461-
stream_join_dynamic #(NoMstPorts) i_b_stream_join (
460+
cc_stream_join_dynamic #(NoMstPorts) i_b_stream_join (
462461
.inp_valid_i(mst_b_valids & {NoMstPorts{outstanding_multicast}}),
463462
.inp_ready_o(mst_b_readies_join),
464463
.sel_i (multicast_select_q),
@@ -475,7 +474,7 @@ module axi_mcast_demux_simple #(
475474

476475
// All fields of B other than RESP can be taken from any slave (need not be merged).
477476
// We use a priority encoder to take them from the first addressed slave.
478-
lzc #(
477+
cc_lzc #(
479478
.WIDTH ( NoMstPorts ),
480479
.MODE ( 1'b0 ) // Trailing zero mode
481480
) i_mst_b_valids_tzc (
@@ -551,7 +550,7 @@ module axi_mcast_demux_simple #(
551550
end
552551

553552
// this ff is needed so that ar does not get de-asserted if an atop gets injected
554-
`FFLARN(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni)
553+
`FFL(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni)
555554

556555
if (UniqueIds) begin : gen_unique_ids_ar
557556
// If the `UniqueIds` parameter is set, each read transaction has an ID that is unique among
@@ -589,10 +588,10 @@ module axi_mcast_demux_simple #(
589588
// R Channel
590589
//--------------------------------------
591590

592-
logic [cf_math_pkg::idx_width(NoMstPorts)-1:0] r_idx;
591+
logic [cc_pkg::idx_width(NoMstPorts)-1:0] r_idx;
593592

594593
// Arbitration of the different r responses
595-
rr_arb_tree #(
594+
cc_rr_arb_tree #(
596595
.NumIn ( NoMstPorts ),
597596
.DataType ( logic ),
598597
.AxiVldRdy( 1'b1 ),

0 commit comments

Comments
 (0)