Skip to content

Latest commit

 

History

History
19 lines (16 loc) · 490 Bytes

File metadata and controls

19 lines (16 loc) · 490 Bytes

SPI Master IP Regression Results

Date: 2026-01-02 16:26:49

Test Name Status
Lint (SV/Verilator) PASS
Native Sim (SV/Icarus) PASS
Native Sim (VHDL/GHDL) PASS
Formal Verification (SymbiYosys) PASS
Native Sim (SV/ModelSim) PASS
Native Sim (VHDL/ModelSim) PASS
Native Sim (SV/Xilinx) PASS
Native Sim (VHDL/Xilinx) PASS
Cocotb Verification PASS
UVM Verification PASS

Detailed Results

Passed: 10/10